MAX3679A 查看數據表（PDF） - Microsemi Corporation
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MAX3679A Datasheet PDF : 12 Pages
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+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless other-
wise noted.) (Notes 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Current
Input Low Current
IIH
VIN = VCC
IIL
VIN = 0V
REF_IN SPECIFICATIONS (Input DC- or AC-Coupled)
Reference Clock Frequency
PLL enabled
PLL bypassed
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input High Current
Input Low Current
IIH
VIN = VCC
IIL
VIN = 0V
Reference Clock Duty Cycle
PLL enabled
Input Capacitance
QA_C SPECIFICATIONS
Output High Voltage
VOH QA_C sourcing 12mA
Output Low Voltage
VOL QA_C sinking 12mA
Output Rise/Fall Time
(Notes 3, 6)
Output Duty-Cycle Distortion
PLL enabled
PLL bypassed (Note 5)
Output Impedance
CLOCK OUTPUT AC SPECIFICATIONS
VCO Frequency Range
80
μA
-80
μA
25
MHz
320
2.0
V
0.8
V
240
μA
-240
μA
30
70
%
2.5
pF
2.6
V
0.4
V
250 500 1000
ps
42
50
58
%
40
60
14
625
MHz
Random Jitter (Note 7)
12kHz to 20MHz
RJRMS
1.875MHz to 20MHz
0.36
0.14
1.0
psRMS
Deterministic Jitter Due to
Supply Noise
LVPECL output (Notes 7, 8, 9)
5.0
psP-P
Spurs Induced by Power-Supply
Noise (Notes 7, 9, 10)
LVPECL output
LVCMOS output
-59
dBc
-47
Nonharmonic and Subharmonic
Spurs
-70
dBc
Output Skew
Between QB0 and QB1
Between QA and QB0 or QB1,
PECL outputs
15
ps
20
Clock Output SSB Phase Noise
at 125MHz (Note 11)
f = 1kHz
f = 10kHz
f = 100kHz
f = 1MHz
f > 10MHz
-124
-125
-130
-145
-153
dBc/Hz
Note 1: A series resistor of up to 10.5Ω is allowed between VCC and VCCA for filtering supply noise when system power-supply
tolerance is VCC = 3.3V ±5%. See Figure 2.
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