FX365C 查看數據表（PDF） - CML Microsystems Plc
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FX365C Datasheet PDF : 9 Pages
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Pin Number
Function
FX365C DW, J, LG and LS package styles
1
V : Positive supply rail. A single stable supply is required; levels and voltages within the FX365C are
DD
dependent upon this supply.
This pin should be decoupled to VSS by a capacitor located close to the pin.
2
Xtal/CIock: Input to the on-chip inverter; used with a 1.0MHz Xtal or external clock source.
3
Xtal: Output of the on-chip clock oscillator inverter.
4
Load/Latch: Controls 8 on-chip latches and is used to latch Rx/Tx, PTL, D0 - D5. This pin is internally
pulled to VDD. A logic ‘1’ applied to this input places the 8 latches into a 'transparent' mode. A logic ‘0’
applied to this input places the 8 latches into the ‘latched’ mode.
In parallel mode data is loaded and latched by a logic ‘1’ to ‘0’ transition (see Figure 4a).
In serial mode data is loaded and latched by a ‘0’ to ‘1’ to ‘0’ strobe pulse on this pin (see Figure 4b).
5
D5/Serial Enable 1: Data input D5 (Parallel Mode); Serial Enable 1 (Serial Mode).
A logic ‘l’ applied to this input, together with a logic ‘0’ applied to D4/Serial Enable 2, will put the device
into 'Serial Mode' (see Figure 4b). This pin is internally pulled to V .
DD
6
D4/Serial Enable 2: Data input D4 (Parallel Mode); Serial Enable 2 (Serial Mode).
A logic ‘0’ applied to this input, together with a logic ‘1’ applied to D /Serial Enable 1, will place the
5
device into ‘Serial Mode’ (see Figure 4b). This pin internally pulled to VDD.
7
D /Serial Data: Data input D (Parallel Mode); Serial Data Input (Serial Mode).
3
3
In Serial Mode this pin becomes the serial data input for D5 - D0, Rx/Tx, PTL (see Figure 4b). D5 is
clocked-in first and PTL last. This pin internally pulled to VDD.
8
D2/Serial Clock: Data input D2 (Parallel Mode); Serial Clock Input (Serial Mode).
In Serial Mode this pin becomes the Serial Clock input. Data is clocked on the positive-going edge
(see Figure 4b). This pin is internally pulled to V .
DD
9
D1: Data input D1 (Parallel Mode); Not Used (Serial Mode). This pin is internally pulled to VDD.
10
D : Data input D (Parallel Mode); Not Used (Serial Mode). This pin is internally pulled to V .
0
0
DD
11
VSS: Negative supply (GND).
12
Decode Comparator Ref. (I/P): Internally biased to VDD/3 or 2VDD/3 via 1.0MΩ resistors depending
on the logical state of the Tone Decode Output pin, this input provides the decode comparator
reference voltage; switching of bias voltages provides hysteresis to reduce 'chatter' under marginal
conditions. Tone Decode Output = logic ‘1’ will place this input to 2VDD/3 bias, a logic ‘0’ will bias this
input to VDD/3.
2
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