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ISPLSI1016E(1998) 查看數據表(PDF) - Lattice Semiconductor

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产品描述 (功能)
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ISPLSI1016E
(Rev.:1998)
Lattice
Lattice Semiconductor Lattice
ISPLSI1016E Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Specifications ispLSI 1016E
Internal Timing Parameters1
PARAMETER #2
DESCRIPTION
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
GRP
tgrp1
tgrp4
tgrp8
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
tgrp16
32 GRP Delay, 16 GLB Loads
GLB
t4ptbpc
t4ptbpr
34 4 Product Term Bypass Path Delay (Combinatorial)
35 4 Product Term Bypass Path Delay (Registered)
t1ptxor
t20ptxor
txoradj
tgbp
36 1 Product Term/XOR Path Delay
37 20 Product Term/XOR Path Delay
38 XOR Adjacent Path Delay 3
39 GLB Register Bypass Delay
tgsu
tgh
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
tgco
42 GLB Register Clock to Output Delay
tgro
tptre
tptoe
tptck
43 GLB Register Reset to Output Delay
44 GLB Product Term Reset to Register Delay
45 GLB Product Term Output Enable to I/O Cell Delay
46 GLB Product Term Clock Delay
ORP
torp
torpbp
47 ORP Delay
48 ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice hard macros.
-125
-100
-80
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
0.3 0.4 0.6 ns
1.8 2.4 3.6 ns
3.0 3.5 4.5
ns
-0.3 -0.4 -0.6
ns
4.0 5.0 7.5 ns
4.0 5.0 7.5 ns
2.2 2.6 3.9 ns
1.8 1.9 2.9 ns
1.9 2.2 3.3 ns
2.1 2.5 3.8 ns
2.4 3.1 4.7 ns
3.9 5.7 8.1 ns
3.9 5.6 7.3 ns
4.4 6.1 7.1 ns
4.4 6.1 8.2 ns
4.4 6.6 8.3 ns
1.0 1.6 1.9 ns
0.2 0.2 -0.6
ns
1.5 2.5 4.3
ns
1.8 1.9 2.9 ns
4.4 6.3 7.0 ns
3.5 5.1 7.2 ns
5.5 7.1 9.7 ns
3.2 3.5 4.8 5.3 6.8 7.5 ns
1.0 1.0 1.5 ns
0.0
0.0
0.0 ns
Table 2-0036-16/125,100, 80
6

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