LCK4802 查看數據表（PDF） - Agere -> LSI Corporation

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LCK4802

Low-Voltage PECL Differential Clock

Agere -> LSI Corporation 

Preliminary Data Sheet

July 2001

LCK4802

Low-Voltage PECL Differential Clock

Pin Information (continued)

Table 3. Function Control

Control Pin

REF_SEL

TESTM

PLLREF_EN

PLL_BYPASS

EXTFB_EN

PCLK0_EN

PCLK1_EN

RESET

SEL[4:0]

0

PECL_CLK.

M divider test mode enabled.

Disable the input to the PLL and reset

the M divider.

Outputs fed by input reference or M

divider.

External feedback enabled.

PCLK0 = low, PCLK0 = high.

PCLK1 = low, PCLK1 = high.

Resets feedback N divider.

See Table 2 on page 4.

1

PECL_CLK.

Reference fed to bypass MUX.

Enable the input to the PLL.

Outputs fed by VCO.

Internal feedback enabled.

PCLK0 = high, PCLK0 = low.

PCLK1 = high, PCLK1 = low.

Feedback enabled.

See Table 2 on page 4.

Absolute Maximum Characteristics

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are

absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in

excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for

extended periods can adversely affect device reliability.

Table 4. Absolute Maximum Ratings

Parameter

Power Supply

Input Voltage

Write Current

Storage Temperature

Symbol

VDDD/VDDA

VDDPECL

VIN

IIN

TS

Min

–0.5

–0.5

–0.5

–1

–50

Typical

—

—

—

—

—

Max

4.4

4.4

VDDD + 0.3

1

150

Unit

V

V

mA

°C

Agere Systems Inc.

5

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