SST30VR041 查看數據表（PDF） - Silicon Storage Technology
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SST30VR041 Datasheet PDF : 10 Pages
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4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo
SST30VR041 / SST30VR043
Preliminary Specifications
Address
ROMCS#
OE#
TRC
TAA
TCO
TLZ(2)
TOE
THZ(1,2)
TOHZ(1)
Data Out
High-Z
TOLZ
Data Valid
TOH
FIGURE
Notes:
1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition
and are referenced to the VOH or VOL.
2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given
device and from device to device.
5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# & OE# CONTROLLED)
381 ILL F03.0
II. SRAM Operation (ROMCS# = VIH)
TABLE 6: READ CYCLE TIMING PARAMETERS VDD = 3.0V±0.3
SST30VR041-70
Symbol Parameter
Min
Max
TRC
Read Cycle Time
TAA
Address Access Time
TCO
Chip Select to Output
TLZ
Chip Select to Low-Z Output
THZ
Chip Disable to High-Z Output
TOH
Output Hold from Address Change
70
70
70
0
25
10
TABLE 7: WRITE CYCLE TIMING PARAMETERS VDD = 3.0V±0.3
SST30VR041-70
Symbol Parameter
Min
Max
TWC
TCW
TAW
TAS
TWP
TWR
TWHZ
TDW
TDH
TOW
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
70
60
60
0
60
0
30
30
0
0
©2001 Silicon Storage Technology, Inc.
6
SST30VR041/043-150
Min
Max
150
150
150
0
30
15
Units
ns
ns
ns
ns
ns
ns
T6.2 381
SST30VR041/043-150
Min
Max
150
120
120
0
120
0
60
60
0
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T7.2 381
S71134-02-000 4/01 381
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