SST30VR041 查看數據表（PDF） - Silicon Storage Technology
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SST30VR041 Datasheet PDF : 10 Pages
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4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo
SST30VR041 / SST30VR043
Preliminary Specifications
Address
OE#/RAMCS#
TWC
TAW
TCW(2)
TWR(4)
WE#
TAS(3)
TWP(1)
TOH
Data In
Data Out
High-Z
TWHZ(5)
TDW
Data Valid
High-Z (6)
TOW
TDH
(7)
(8)
381 ILL F06.0
Notes:
1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among
RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high,
TWP is measured from the beginning of write to the end of write.
2. TCW is measured from the later of RAMCS# going low to the end of write.
3. TAS is measured from the address valid to the beginning of write.
4. TWR is measured from the end of write to the address change.
5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state.
7. DOUT is the same phase of the latest written data in this write cycle.
8. DOUT is the read data of new address
9. ROMCS# = VIH
FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM
TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE
Address Inputs
X2
AMS3-A0
AMS3-A0
Only AMS4-A0 are valid
Only AMS4-A0 are valid
ROMCS#
H
L
L
H
H
OE#/RAMCS#1
(Pin 32)
H
OE# (H)
OE# (L)
RAMCS# (L)
RAMCS# (L)
1. OE# & RAMCS# are pin-shared
2. X means Don’t Care.
3. For ROM: AMS = A18 for SST30VR041 and SST30VR043
4. For RAM: AMS = A16 for SST30VR041, A18-A17 must be fixed to “L” or “H”
AMS = A14 for SST30VR043, A18-A15 must be fixed to “L” or “H”
WE#
X
X
X
H
L
DQ7-DQ0
Z
Z
DOUT
DOUT
DIN
Standby
Output Floating
ROM Read
RAM Read
RAM Write
T8.3 381
©2001 Silicon Storage Technology, Inc.
8
S71134-02-000 4/01 381
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