VBUS05A1-SD0 查看數據表（PDF） - Vishay Semiconductors
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VBUS05A1-SD0
Low Capacitance Bidirectional Symmetrical (BiSy) Single Line ESD-Protection Diode in Silicon Package
Vishay Semiconductors
VBUS05A1-SD0 Datasheet PDF : 9 Pages
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www.vishay.com
0.8
f = 1MHz
0.7
Pin 1-2 or Pin 2-1
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
1
2
3
4
5
22702
VR (V)
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
10
9
8
7
6
5
4
3
2
1
0
0.01 0.1
22703
Pin 1-2 or Pin 2-1
1 10 100 1000 10 000
IR in µA
Fig. 4 - Typical Reverse Voltage VR vs. Reverse Current IR
18
Pin 1-2 or Pin 2-1
16
14
12
10
8
6
VC
4
2 Measured acc. to IEC 61000-4-5
(8/20 μs - wave form)
0
0
1
2
3
22704
IPP (A)
Fig. 5 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
VBUS05A1-SD0
Vishay Semiconductors
140
Pin 1-2 or Pin 2-1
120
acc. IEC 61000-4-2
10
+8 kV +8k
contact discharge
80
60
40
20
0
-20
-10 0 10 20 30 40 50 60 70 80 90
22705
t (ns)
Fig. 6 - Typical Clamping Performance at 8 kV Contact Discharge
(acc. IEC 61000-4-2)
18
Pin 1-2 or Pin 2-1
16 Transmission Line Pulse (TLP)
tp = 100 ns
14
(Average between
12
55 ns and 95 ns)
10
8
6
4
2 VC-TLP = 1.29 Ω x ITLP + 11.86 V
0
(RDYN = 1.29 Ω)
0 5 10 15 20 25 30 35
22730
VC-TLP in V
Fig. 7 - Typical Clamping Voltage at 100 ns Transmission Line Pulse
(TLP)
0 dB
-1 dB
-2 dB
Pin 1-2 or Pin 2-1
-5 V < VR < +5 V
-3 dB
-4 dB
-5 dB
1.0E+07
22707
1.0E+08
1.0E+09
f (Hz)
Fig. 8 - Typical Attenuation in a 50 System
Rev. 1.2, 19-Nov-13
3
Document Number: 85245
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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