SN8P0111S 查看數據表（PDF） - Sonix Technology Co., Ltd
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SN8P0111S Datasheet PDF : 3 Pages
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4. BLOCK DIAGRAM
PC
IR
FLAGS
OTP
ROM
H-OSC
TIMING GENERATOR
SN8P021X/8P011X
PORT 0
ALU
ACC
INTERRUPT
CONTROL
RAM
SYSTEM REGISTER
TIMER & COUNTER
PORT 1
PORT 2
5. PIN DESCRIPTION
PIN NAME
P1.0 ~ P1.3
RST/VPP
VDD, VSS
P2.0 ~ P2.7
XIN
XOUT
P0.0 / INT0
TYPE
I/O
I
P
I/O
I
O
I
DESCRIPTION
Port 1.0 ~ Port 1.3 bi-direction pins.
System reset inputs pin. Schmitt trigger structure, active “low”, normal stay to “high”.
During program op-code, this pin be pull to 12.5Vdc to reset internal address counter and to
write data into OTP-ROM.
Power supply input pins.
Port 2.0 ~ Port 2.7 bi-direction pins.
Oscillator input pin.
Oscillator output pin.
Port 0.0 and INT0 trigger pin with schmitt trigger structure.
Note : In order to reduce power consumption, the following procedure must be setup.
a). In the SN8P0211/8P0111 version, P1.2 ~ P1.3 must be programmed to input mode with pull up resistor.
SONiX TECHNOLOGY CO., LTD
Page 2
Preliminary
January 2000
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