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854110AKILF

2.5V Differential LVDS Clock Buffer

Integrated Device Technology 

ICS854110I Data Sheet

2.5V DIFFERENTIAL LVDS CLOCK BUFFER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value

of the fundamental. This ratio is expressed in decibels (dBm) or a

ratio of the power in the 1Hz band to the power in the fundamental.

When the required offset is specified, the phase noise is called a dBc

value, which simply means dBm at a specified offset from the

fundamental. By investigating jitter in the frequency domain, we get

a better understanding of its effects on the desired application over

the entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 125MHz

12kHz to 20MHz = 0.291ps (typical)

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements have

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

The source generator used is, "Rohde & Schwarz SMA 100A Signal

Generator into a HP 8133A 3GHz Pulse Generator".

ICS854110AKI REVISION B JANUARY 27, 2011

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©2011 Integrated Device Technology, Inc.

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