SC4000 查看數據表（PDF） - Philips Electronics
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SC4000 Datasheet PDF : 52 Pages
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Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC4000
Pin Description (continued)
Pin Name
DRQ_R
or
TEST_OUT_0
DRQ_T
or
TEST_OUT_1
SCLKX2N
SCLKX2NA
SCLK
Input/Output
O
Pin Number
99
O
100
I/O
46
I/O
47
I/O
49
SCLKA
I/O
50
SREF_8K
I/O
51
SREF_8KA
I/O
52
FSYNCN
I/O
54
FSYNCNA
I/O
55
CLKFAIL
I/O
56
CLKFAILA
I/O
58
Pin Description
(TTL Output) Receive DMA Request. This pin is reserved for a future internal HDLC controller. Otherwise, in Test
Mode (TEST=1), this is a NANDed gate test chain 0 output.
(TTL Output) Transmit DMA Request. This pin is reserved for a future internal HDLC controller. Otherwise, in Test
Mode (TEST=1), this is a NANDed gate test chain 1 output.
(SCbus Bi-directional) SCbus System clock x 2.
(SCbus Bi-directional) SCbus Alternate System clock x 2.
(SCbus Bi-directional) SCbus System clock. This can be programmed to either 2.048, 4.096 or 8.192 MHz.
Set C_0 = 1 to enable the SCLK output driver as master mode.
Set C_0 = 0 to disable the SCLK output driver as slave mode.
(SCbus Bi-directional) SCbus Alternate System clock.
(SCbus Bi-directional) SCbus 8 KHz Reference.
If C_46 = 1, the SREF_8K output is enabled at SCbus
If C_46 = 0, the SREF_8K output is disabled at SCbus
(SCbus Bi-directional) SCbus 8 KHz Alternate Reference.
(SCbus Bi-directional) SCbus 8 KHz Frame Synchronization signal.
Set C_0 = 1 to enable the FSYNCN output driver as master mode.
Set C_0 = 0 to disable the FSYNCN output driver as slave mode.
(SCbus Bi-directional) SCbus 8 KHz Alternate Frame Synchronization signal.
(SCbus Bi-directional) SCbus System Clock Fail signal.
(SCbus Bi-directional) SCbus Alternate System Clock Fail signal.
SD_[0:15]
I/O
59,60,62,63,
64,66,67,68,
70,71,72,74,
75,76,77,79
(SCbus Bi-directional) These are SCbus Serial Data Streams can be programmed to 2.048, 4.096 or 8.192 Mb/s
data rates.
MC
I/O
80
(SCbus Bi-directional Open Collector) SCbus Message Channel.
MCA
I/O
81
(SCbus Bi-directional Open Collector) SCbus Alternate Message Channel.
L_CLK
I/O
83
(TTL Bi-directional) Local bus Clock Output. It can be programmed to: 2.048, 4.096 or 8.192 MHz if set C_28 = 0.
4.096, 8.192 or 16.384 MHz if set C_28 = 1.
L_FS
I/O
84
(TTL Bi-directional) Local bus 8 KHz Frame Synchronization Output.
S0_[3:0]
I/O
90,88,87,86
(TTL Bi-directional) Local Bus Serial Output Data Streams. It can be programmed to 2.048, 4.096 or 8.192 Mb/s
data rates.
MC_CLK
I/O
11
(TTL Bi-directional) Message Channel Data Clock. This pin is a 2.048 MHz output. The clock duty cycle can be
programmed by C_14 bit.
RXD
I/O
10
(TTL Bi-directional) Message Channel Receive Data. This pin is for the SCbus message channel receive data output
line.
VDD
Power
8,13,29,37,48,
+5 Volt Power Supply.
61,65,78,85,89
VSS
Power
3,18,23,33,41,
Ground.
45,53,57,69,73,
82,93,97
Note: In Test mode (TEST=1), every pin except VDD/VSS/X_OUT/DRQ_R/DRQ_T is configured as input.
2000 Sep 07
11
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