CS51033 查看數據表（PDF） - ON Semiconductor
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CS51033 Datasheet PDF : 10 Pages
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CS51033
APPLICATIONS INFORMATION
DESIGNING A POWER SUPPLY WITH THE CS51033
Specifications
• VIN = 3.3 V ±10% (i.e. 3.63 V max., 2.97 V min.)
• VOUT = 1.5 V ±2.0%
• IOUT = 0.3 A to 3.0 A
• Output ripple voltage < 33 mV.
• FSW = 200 kHz
1) Duty Cycle Estimates
Since the maximum duty cycle D, of the CS51033 is
limited to 80% min., it is best to estimate the duty cycle for
the various input conditions to see that the design will work
over the complete operating range.
The duty cycle for a buck regulator operating in a
continuous conduction mode is given by:
D
+
VOUT
VIN *
) VD
VSAT
where:
VSAT = RDS(ON) × IOUT Max.
In this case we can assume that VD = 0.6 V and VSAT =
0.6 V so the equation reduces to:
D
+
VOUT
VIN
From this, the maximum duty cycle DMAX is 53%, this
occurs when VIN is at it’s minimum while the minimum duty
cycle DMIN is 0.35%.
2) Switching Frequency and On and Off Time
Calculations
FSW = 200 kHz. The switching frequency is determined
by COSC, whose value is determined by:
COSC +
FSW
ǒ Ǔ 95
^ 470 pF
ǒ Ǔ ǒ Ǔ 1 *
FSW
3 106
*
30 103 2
FSW
T
+
1.0
FSW
+
5.0
ms
TON(MAX) + 5.0 ms 0.53 + 2.65 ms
TON(MIN) + 5.0 ms 0.35 + 1.75 ms
TOFF(MAX) + 5.0 ms * 0.7 ms + 4.3 ms
3) Inductor Selection
Pick the inductor value to maintain continuous mode
operation down to 0.3 Amps.
The ripple current DI = 2 × IOUT(MIN) = 2 × 0.3 A = 0.6 A.
LMIN
+
VOUT
)
VD
DI
TOFF(MAX)
+
2.1
V
0.6
4.3
A
ms
^
15
mH
The CS51033 will operate with almost any value of
inductor. With larger inductors the ripple current is reduced
and the regulator will remain in a continuous conduction
mode for lower values of load current. A smaller inductor
will result in larger ripple current. The core must not saturate
with the maximum expected current, here given by:
IMAX
+
IOUT )
2.0
DI
+
3.0
A
)
0.6
Ań2.0
+
3.3
A
4) Output Capacitor
The output capacitor limits the output ripple voltage. The
CS51033 needs a maximum of 15 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak−to−peak is given by:
CO + 8.0
DI
FSW
DV
+
8.0
(200
0.6 A
103 Hz) (33
10*3 V) ^ 11.4 mF
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak−to−peak is:
ESR
+
DV
DI
+
50
10*3
0.6 A
+
55
mW
The output capacitor should be chosen so that its ESR is
at least half of the calculated value and the capacitance is at
least ten times the calculated value. It is often advisable to
use several capacitors in parallel to reduce ESR.
Low impedance aluminum electrolytic, tantalum or
organic semiconductor capacitors are a good choice for an
output capacitor. Low impedance aluminum are the
cheapest but are not available in surface mount at present.
Solid tantalum chip capacitors are available from a number
of suppliers and offer the best choice for surface mount
applications. The capacitor working voltage should be
greater than the output voltage in all cases.
5) VFB Divider
ǒ Ǔ ǒ Ǔ VOUT + 1.25 V
R1 ) R2
R2
+ 1.25
V
R1
R2
)
1.0
The input bias current to the comparator is 4.0 mA. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this gives a divider current of 1.0 mA and simplifies
the calculations.
1.5 V
1.0 mA
+
R1
)
R2
+
1.5
kW
Let R2 = 1.0 k
Rearranging the divider equation gives:
ǒ Ǔ ǒ Ǔ R1 + R2
VOUT
1.25
*
1.0
+ 1.0 kW
1.5 V
1.25
+ 200 W
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