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HCF4029B 查看數據表(PDF) - STMicroelectronics

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HCF4029B Datasheet PDF : 12 Pages
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HCF4029B
signal is normally high and the counter reaches its
maximum count in the UP mode or the minimum
count in the DOWN mode provided the CARRY-IN
signal is low. The CARRY-IN signal in the low
state can thus be considered a CLOCK ENABLE.
The CARRY-IN terminal must be connected to
VSS when not in use. Binary counting is
accomplished when the BINARY/DECODE input
is high; the counter counts in the decade mode
when the BINARY/DECADE input is low. The
counter counts Up when to UP/DOWN INPUT is
high, and Down when the UP/DOWN INPUT is
low. Multiple packages can be connected in either
a parallel clocking or a ripple clocking
arrangement. Parallel clocking provides
synchronous control and, hence, a faster
response from all counting outputs. Ripple
clocking allows for longer clock input rise and fall
times.
IINPUT EQUIVALENT CIRCUIT
FUNCTIONAL DIAGRAM
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
15
5
9
10
1
4, 12, 13, 3
6, 11, 14, 2
7
8
16
CLOCK Clock Input
CARRY IN Carry In Input
BINARY/
DECADE
Binary / Decade Select
UP/DOWN Up/Down Select
PRESET
ENABLE
Preset Enable Input
JAM1 to JAM4 Jam Input Signals
Q1 to Q4 Q Outputs
CARRY OUT Carry Out Outputs
VSS
Negative Supply Voltage
VDD
Positive Supply Voltage
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