SL4052BD 查看數據表（PDF） - System Logic Semiconductor

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SL4052BD

Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS

System Logic Semiconductor 

SL4052B

DC ELECTRICAL CHARACTERISTICS Digital Section

Symbol

Parameter

Test Conditions

VIH

Minimum High-Level

VIS=VCC thru 1kΩ

Input Voltage, Channel- VEE=GND

Select or Enable Inputs IIS<2µA on all OFF Chanels

RL=1kΩ to GND

VIL

Maximum Low -Level VIS=VCC thru 1kΩ

Input Voltage, Channel- VEE=GND

Select or Enable Inputs IIS<2µA on all OFF Chanels

RL=1kΩ to GND

IIN

Maximum Input

Leakage Current,

Channel-Select or

Enable Inputs

VIN=VCC or GND

ICC

Maximum Quiescent

Channel Select = VCC or GND

Supply Current (per

Package)

VCC

Guaranteed Limit

V ≥ -55 ≤ 25 ≤ 125 Unit

°C

°C

°C

5 3.5 3.5 3.5 V

10 7

7

7

15 11

11 12

5 1.5 1.5 1.4 V

10 3

3

3

15 4

4

4

18 ±0.1 ±0.1 ±1.0 µA

5

5

10 10

15 20

20 100

5

150 µA

10 300

20 600

100 3000

DC ELECTRICAL CHARACTERISTICS Analog Section

VCC

Symbol

Parameter

Test Conditions

V

RON Maximum “ON” Resistance VEE=GND=0

5

VIS = GND to VCC

10

15

∆RON Maximum Difference in

VEE=GND=0

5

“ON” Resistance Between

10

Any Two Channels in the

15

Same Package

IOFF Maximum Off- Channel

VEE=GND=0

18

Leakage Current, Any One

Channel

Maximum Off- Channel

VEE=GND=0

18

Leakage Current, Common

Channel

Guaranteed Limit

≥ -55

°C

≤ 25 ≤ 125 Unit

°C

°C

800

1050 1300 Ω

310

400 550

200

240 320

-

10

-

Ω

-

15

-

-

5

-

±100 ±100 ±1000 nA

±100 ±100 ±1000

SLS

System Logic

Semiconductor

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