UT54LVDSC031-UCA 查看數據表（PDF） - Aeroflex UTMC
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UT54LVDSC031-UCA Datasheet PDF : 12 Pages
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DIN1
DOUT1+
DOUT1-
EN
DOUT2-
DOUT2+
DIN2
VSS
1
16
2
15
3
14
UT54LVDSC031
4
Driver
13
5
12
6
11
7
10
8
9
VDD
DIN4
DOUT4+
DOUT4-
EN
DOUT3-
DOUT3+
DIN3
Figure 2. UT54LVDSC031 Pinout
APPLICATIONS INFORMATION
The UT54LVDSC031 driver’s intended use is primarily in an
uncomplicated point-to-point configuration as is shown in
Figure 3. This configuration provides a clean signaling
environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media such as a
standard twisted pair cable, a parallel pair cable, or simply PCB
traces. Typically, the characteristic impedance of the media is
in the range of 100Ω. A termination resistor of 100Ω should be
selected to match the media and is located as close to the receiver
input pins as possible. The termination resistor converts the
current sourced by the driver into voltages that are detected by
the receiver. Other configurations are possible such as a multi-
receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance discontinuities,
as well as ground shifting, noise margin limits, and total
termination loading must be taken into account.
TRUTH TABLE
Enables
EN
EN
L
H
All other combinations
of ENABLE inputs
Input
DIN
X
L
H
Output
DOUT+
Z
DOUT-
Z
L
H
H
L
PIN DESCRIPTION
Pin No.
1, 7, 9, 15
Name
DIN
2, 6, 10, 14 DOUT+
3, 5, 11, 13 DOUT-
4
EN
12
EN
16
VDD
8
VSS
Description
Driver input pin, TTL/CMOS
compatible
Non-inverting driver output pin,
LVDS levels
Inverting driver output pin,
LVDS levels
Active high enable pin, OR-ed
with EN
Active low enable pin, OR-ed
with EN
Power supply pin, +5V + 10%
Ground pin
ENABLE
DATA
INPUT
1/4 UT54LVDSC031
RT 100Ω
1/4 UT54LVDSC031
+
- DATA
OUTPUT
Figure 3. Point-to-Point Application
The UT54LVDSC031 differential line driver is a balanced
current source design. A current mode driver, has a high output
impedance and supplies a constant current for a range of loads
(a voltage mode driver on the other hand supplies a constant
voltage for a range of loads). Current is switched through the
load in one direction to produce a logic state and in the other
direction to produce the other logic state. The current mode
requires (as discussed above) that a resistive termination be
employed to terminate the signal and to complete the loop as
shown in Figure 3. AC or unterminated configurations are not
allowed. The 3.4mA loop current will develop a differential
voltage of 340mV across the 100Ω termination resistor which
the receiver detects with a 240mV minimum differential noise
margin neglecting resistive line losses (driven signal minus
receiver threshold (340mV - 100mV = 240mV)). The signal is
centered around +1.2V (Driver Offset, VOS) with respect to
ground as shown in Figure 4. Note: The steady-state voltage
(VSS) peak-to-peak swing is twice the differential voltage (VOD)
and is typically 680mV.
2
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