FIN1101 查看數據表（PDF） - Fairchild Semiconductor
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FIN1101 Datasheet PDF : 6 Pages
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AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
(Note 3)
Units
tPLHD
Differential Propagation Delay
LOW-to-HIGH
0.75
1.1
1.75
ns
tPHLD
Differential Propagation Delay
HIGH-to-LOW
RL = 100 Ω, CL = 5 pF,
VID = 200 mV to 450 mV,
0.75
1.1
1.75
ns
tTLHD
Differential Output Rise Time (20% to 80%)
VIC = |VID|/2 to (VCC− (VID/2),
0.29
0.40
0.58
ns
tTHLD
Differential Output Fall Time (80% to 20%)
Duty Cycle = 50%,
0.29
0.40
0.58
ns
tSK(P)
Pulse Skew |tPLH - tPHL|
See Figure 3 and Figure 4
0.01
0.2
ns
tSK(PP)
Part-to-Part Skew (Note 4)
0.5
ns
fMAX
Maximum Frequency (Note 5)(Note 6)
400
800
MHz
tPZHD
Differential Output Enable Time from Z to HIGH
2.1
5
ns
tPZLD
Differential Output Enable Time from Z to LOW RL = 100 Ω, CL = 5 pF,
2.3
5
ns
tPHZD
Differential Output Disable Time from HIGH to Z See Figure 2 and Figure 3
1.5
5
ns
tPLZD
tDJ
Differential Output Disable Time from LOW to Z
LVDS Data Jitter,
VID = 300 mV, PRBS = 223 − 1,
Deterministic
VIC = 1.2V at 800 Mbps
1.8
5
ns
85
135
ps
tRJ
LVDS Clock Jitter, Random
(RMS)
VID = 300 mV
VIC = 1.2 V at 400 MHz
2.1
3.5
ps
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V, VID = 300mV, VIC = 1.2V unless otherwise specified.
Note 4: tSK(PP) is the magnitude of the difference in differential propagation delay times between identical channels of two devices switching in the same
direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test cir-
cuits.
Note 5: Passing criteria for maximum frequency is the output VOD > 200 mV and the duty cycle is 45% to 55% with all channels switching.
Note 6: Output loading is transmission line environment only; CL is < 1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions and
Propagation I and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
Note A: All LVDS input pulses have frequency = 10MHz, tR or tF < = 0.5 ns
Note B: CL includes all probe and test fixture capacitances
FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit
3
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