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AD598A

LVDT Signal Conditioner

Analog Devices 

AD598

DESIGN PROCEDURE

DUAL SUPPLY OPERATION

Figure 7 shows the connection method with dual ±15 volt power

supplies and a Schaevitz E100 LVDT. This design procedure

can be used to select component values for other LVDTs as

well. The procedure is outlined in Steps 1 through 10 as follows:

1. Determine the mechanical bandwidth required for LVDT

position measurement subsystem, fSUBSYSTEM. For this

example, assume fSUBSYSTEM = 250 Hz.

2. Select minimum LVDT excitation frequency, approximately

10 × fSUBSYSTEM. Therefore, let excitation frequency = 2.5 kHz.

3. Select a suitable LVDT that will operate with an excitation

frequency of 2.5 kHz. The Schaevitz E100, for instance, will

operate over a range of 50 Hz to 10 kHz and is an eligible

candidate for this example.

4. Determine the sum of LVDT secondary voltages VA and VB.

Energize the LVDT at its typical drive level VPRI as shown in

the manufacturer’s data sheet (3 V rms for the E100). Set the

core displacement to its center position where VA = VB. Mea-

sure these values and compute their sum VA+VB. For the

E100, VA+VB = 2.70 V rms. This calculation will be used

later in determining AD598 output voltage.

5. Determine optimum LVDT excitation voltage, VEXC. With

the LVDT energized at its typical drive level VPRI, set the

core displacement to its mechanical full-scale position and

measure the output VSEC of whichever secondary produces

the largest signal. Compute LVDT voltage transformation

ratio, VTR.

VTR = VPRI/VSEC

For the E100, VSEC = 1.71 V rms for VPRI = 3 V rms.

VTR = 1.75.

The AD598 signal input, VSEC, should be in the range of

1 V rms to 3.5 V rms for maximum AD598 linearity and

minimum noise susceptibility. Select VSEC = 3 V rms. There-

fore, LVDT excitation voltage VEXC should be:

VEXC = VSEC × VTR = 3 × 1.75 = 5.25 V rms

Check the power supply voltages by verifying that the peak

values of VA and VB are at least 2.5 volts less than the volt-

ages at +VS and –VS.

6. Referring to Figure 7, for VS = ± 15 V, select the value of the

amplitude determining component R1 as shown by the curve

in Figure 8.

7. Select excitation frequency determining component C1.

C1 = 35 µF Hz/fEXCITATION

30

20

Vrms

10

0

0.01

0.1

1

10

R1 – kΩ

100

1000

Figure 8. Excitation Voltage VEXC vs. R1

+15V

6.8µF

0.1µF

6.8µF

0.1µF

–15V

R1

C1

C2

VB

VA

SCHAEVITZ E100

LVDT

1 –VS

2 EXC 1

+VS 20

OFFSET 1 19

3 EXC 2

OFFSET 2 18

4 LEV 1

SIG REF 17

5 LEV 2

SIG OUT 16

6 FREQ 1 FEEDBACK 15

7 FREQ 2 OUT FILT 14

8 B1 FILT

A1 FILT 13

9 B2 FILT

A2 FILT 12

10 VB AD598 VA 11

R4

R3

R2

C4

C3

SIGNAL

REFERENCE

RL

VOUT

NOTE

FOR C1, C2, C3 AND C4 MYLAR

CAPACITORS ARE

RECOMMENDED. CERAMIC

CAPACITORS MAY BE

SUBSTITUTED. FOR R2, R3 AND

R4 USE STANDARD 1%

RESISTORS.

Figure 7. Interconnection Diagram for Dual Supply Operation

–6–

REV. A

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