5962-8957201EC 查看數據表（PDF） - Avago Technologies
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5962-8957201EC Datasheet PDF : 12 Pages
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Typical Specifications
TA = 25° C, VCC = 5 V
Parameter
Symbol Typ.
Units
Test Conditions
Fig.
Note
Resistance (Input-Output)
RI-O
1012
Ω
VI-O = 500 V dc
3, 13
Capacitance (Input-Output) CI-O
1.7
pF
f = 1 MHz
3, 13
Input-Input Insulation
II-I
0.5
nA
≤ 65% Relative Humidity,
11
Leakage Current
VI-I = 500 Vdc, t = 5 s
Resistance (Input-Input)
RI-I
1012
Ω
VI-I = 500 Vdc
11
Capacitance (Input-Input)
CI-I
0.55
pF
Propagation Delay Time of tELH
35
ns
Enable from VEH to VEL
Propagation Delay Time of tEHL
35
ns
Enable from VEL to VEH
Output Rise Time (10-90%) tr
30
ns
Output Fall Time (90-10%)
tf
24
ns
Input Capacitance
CI
60
pF
f = 1 MHz
11
RL = 510 Ω, CL = 15 pF,
6, 7
3, 7
II = 13 mA, VEH = 3 V, VEL = 0 V
6, 7
3, 8
RL = 510 Ω, CL = 15 pF,
3
II = 13 mA
3
f = 1 MHz, VI = 0,
3
PINS 1 to 2 or 5 to 6
Notes:
1. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each isolator. The power supply bus for the isolators
should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to suppress regenerative feedback
via the power supply.
2. Derate linearly at 1.2 mA/°C above TA = 100° C.
3. Each channel.
4. Device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together.
5. The tPLH propagation delay is measured form the 6.5 mA point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of the
output pulse.
6. The tPHL propagation delay is measured from the 6.5 mA point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the
output pulse.
7. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point on the trailing
edge of the output pulse.
8. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point on the leading
edge of the output pulse.
9. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state, i.e.
VOUT > 2.0 V.
10. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state, i.e.
VOUT < 0.8 V.
11. Measured between adjacent input leads shorted together, i.e. between 1, 2 and 4 shorted together and pins 5, 6 and 8 shorted together.
12. No external pull up is required for a high logic state on the enable input.
13. Measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together.
14. Parameters shall be tested as part of device initial characterization and after process changes. Parameters shall be guaranteed to the limits specified
for all lots not specifically tested.
15. Standard parts receive 100% testing at 25° C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25, 125, and -55° C (Subgroups 1
and 9, 2 and 10, 3 and 11, respectively).
7
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