WM8199 查看數據表（PDF） - Cirrus Logic
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WM8199 Datasheet PDF : 32 Pages
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WM8199
INPUT VIDEO SAMPLING
tPER
tMCLKH tMCLKL
MCLK
VSMP
INPUT
tVSMPSU
tVSMPH
tVSU
tVH
VIDEO
Production Data
tRSU
tRH
Figure 3 Input Video Timing
Note:
1.
See Page 20 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C unless otherwise stated.
PARAMETER
MCLK period
SYMBOL
TEST CONDITIONS
MIN
tPER
25
MCLK high period
tMCLKH
11.3
MCLK low period
tMCLKL
11.3
VSMP set-up time
tVSMPSU
5
VSMP hold time
tVSMPH
3
Video level set-up time
tVSU
11
Video level hold time
tVH
4
Reset level set-up time
tRSU
11
Reset level hold time
tRH
4
Notes:
1.
tVSU and tRSU denote the set-up time required after the input video signal has settled.
2.
Parameters are measured at 50% of the rising/falling edge.
TYP
14.1
14.1
OUTPUT DATA TIMING
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK
tPD
OP[7:0]
Figure 4 Output Data Timing
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PD, Rev 4.4, July 2008
9
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