AMIS-30585 查看數據表（PDF） - ON Semiconductor

零件编号

产品描述 (功能)

生产厂家

AMIS-30585

S-FSK PLC Modem

ON Semiconductor 

AMIS-30585

Due to the handling of the low protocol layers in the circuit, the AMIS-30585 provides an innovative architectural split. Thanks to this,

the user has the benefit of a higher level interface of the link to the PLC medium. Compared to an interface at the physical level, the

AMIS-30585 allows faster development of applications. The user just needs to send the raw data to the AMIS-30585 and no longer has

to take care of the protocol detail of the transmission over the specific medium. This last part represents usually 50 percent of the

software development costs.

5.0 Product Ordering Information

Marketing Name

AMIS30585AGA

Ordering Code (Tubes)

0C585-002-XTD

Package

PLCC 28 452 G

Temperature Range

-25°C to +70°C

6.0 Detailed Blocks Description

6.1 Receiver Path Description

The analog signal coming from the line-interface chip is low pass filtered in order to avoid aliasing during the conversion. Then the level

of the signal is automatically adapted by an automatic gain control (AGC) block. This operation maximizes the dynamic range of the

incoming signal. The signal is then converted to its digital representation using sigma delta modulation. From then on, the processing of

the data is done in a digital way. By using dedicated hardware, a direct quadrature demodulation is performed. The signal demodulated

in the base band is then low pass filtered to reduce the nose and reject the image spectrum.

6.2 Transmitter Path Description

For the generation of the tones, the direct digital synthesis of the sine wave frequencies is performed under the control of the

microprocessor. After a signal conditioning step, a digital to analog conversion is performed. As for the receive path, a sigma delta

modulation technique is used. In the analog domain, the signal is low pass filtered, in order to remove the high frequency quantization

noise, and passed to the automatic level controller (ACL) block, where the level of the transmitted signal can be adjusted. The

determination of the signal level is done through the sense circuitry.

6.3 Communication Controller

The communication channel is controlled by an embedded microcontroller. The processor uses the ARM reduced instruction set

computer (RISC) architecture optimized for IO handling. For most of the instructions, the machine is able to perform one instruction per

clock cycle. The microcontroller contains the necessary hardware to implement interrupt mechanisms, timers and is able to perform

byte multiplication over one instruction cycle. The microcontroller is programmed to handle the physical layer (chip synchronization), the

MAC. The program is stored in a masked ROM. The RAM contains the necessary space to store the working data. The back-end

interface is done through the SPI block. This back-end is used for data transmission with the application hardware (concentrator, power

meter, etc.) and for the definition of the modem configuration.

6.4 Clock and Control

According to the IEC standard, the frame data is transmitted at the zero crossing of the mains voltage. In order to recover the

information at the zero crossing, a zero crossing detection of the mains is performed. A phase-locked loop (PLL) structure is used in

order to allow a more reliable reconstruction of the synchronization. This PLL permits as well a safer implementation of the "repetition

with credit" function (also known as chorus transmission). The clock generator makes use of a precise quartz oscillator master. The

clock signals are then obtained by the use of a programmed division scheme. The support circuits are also contained in this block. The

support circuits include the necessary blocks to supply the references voltages for the AD and DA converters, the biasing currents and

power supply sense cells to generate the right power off and startup conditions.

Rev. 2 | Page 3 of 23 | www.onsemi.com

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