AMIS-30585 查看數據表（PDF） - ON Semiconductor

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AMIS-30585

S-FSK PLC Modem

ON Semiconductor 

AMIS-30585

Figure 4: Representation of 5V Safe I/O

7.7 Pin 7, 8, 9, 10, and 11: TDO, TDI, TCK, TMS, and TRSTB

All these pins are part of the JTAG bus interface. It will be connected to the ARM ICE interface box. This provides an access to the

embedded ARM processor. These pins are used during the debugging of the embedded software. Pin characteristics are in-line with

the ARM JTAG interface specification. They will not be described here. Input pins (TDI, TCK, TMS, and TRSTB) contain internal pull-

down resistance. TDO is an output. When not in use, the JTAG interface pins may be left floating.

7.8 Pin 12: TX_DATA

TX_DATA provides the digital output signal not modulated. It gives the logical level associated with the transmitted frequency. So, to

transmit a frequency fs, the TX_DATA logical state is 0 and is present on TX_DATA. To transmit a frequency fm, the TX_DATA logical

state is 1. This output pin is an open drain. An external pull-up resistance is needed to perform the voltage level associated with a

logical one (as for the IOx pins).

7.9 Pin 13: XIN

XIN is the analog input pin of the oscillator. It is connected to the interval oscillator inverter gain stage. The clock signal can be created

either internally with the external crystal and two capacitors or by connecting an external clock signal to XIN. For the internal generation

case, the two external capacitors and crystal are placed as shown in Figure 5. For the external clock connection, the signal is

connected to XIN and XOUT is left unused.

Rev. 2 | Page 7 of 23 | www.onsemi.com

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