HI-8040(1999) 查看數據表（PDF） - Holt Integrated Circuits
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HI-8040 Datasheet PDF : 6 Pages
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HI-8040
FUNCTIONAL DESCRIPTION
INPUT LOGIC
DOUT
CS must be held low to enter data into the shift register.
The data is clocked on the negative edge of CL. LD is nor-
mally held low and only pulsed high when new data is ready
for display. When LD is high the latch is transparent. All four
logic inputs are TTL compatible. A logic "1" at DIN that is
eventually latched to the segment drivers will cause the seg-
ment to be at the opposite voltage level of the BP pin (out of
phase).
BPOSC and BPIN
The user can either make an oscillator to create the
backplane frequency or drive a signal into BPIN leaving
BPOSC open. To make an oscillator, pins BPOSC and
BPIN must be connected together and the appropriate R
and C combination applied (See Figure 1). If the oscillator is
used, the backplane frequency is approximately
fBP = 2561RC. (for R = 180KW & C = 220pF, fBP » 100Hz).
VEE & NEGATIVE VOLTAGE CONVERTER
VEE may be externally driven to a maximum -30V. Alterna-
tively, there is a voltage converter that will provide -21.4 volts
(See Figure 2). If the converter pins are left open circuit, an
on-chip sense resistor will cause shut down of all current
consumption associated with the converter. The converter
will survive a shorted segment condition and continue to
maintain VEE at -20 volts.
The DOUT pin is available from segment 85 for cascading
devices to drive more segments and for verifying the data
integrity. This output can drive 2 TTL loads. It changes on the
positive edge of CL.
AUTOMATIC SEGMENTS OFF
The internal backplane signal is tested continuously to be at
least 10Hz. If the detector senses f<10Hz, then the segments
are forced to the same voltage as the backplane (all segments
in "OFF" state). However, the detector is only functional while
VDD is above the minimum operating voltage specification.
TEST INPUTS
The test functions available are:
T2
T1
Display
0
0
Normal
0
1
All Off
1
0
All On
1
1
Alternating On/Off Segments
The test inputs must be tied to the appropriate logic level for
correct circuit operation.
VDD
R 330KW
IN5818, IN5819
330µh
VSS
10µF
VSS
OSC
RSENSE
Control
VDD
HOLT INTEGRATED CIRCUITS
3-16
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