HI-8110JPQI 查看數據表（PDF） - Holt Integrated Circuits

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HI-8110JPQI

CMOS HIGH VOLTAGE DISPLAY DRIVER

Holt Integrated Circuits 

HI-8010/HI-8110 Series

FUNCTIONAL DESCRIPTION

Whenever a Logic "0" is applied to the Chip Select (CS)

input, one bit of data is clocked into the shift register from the

serial data input (DIN) with each negative transition of the

Clock (CL) input. CS is internally tied to VSS on some

versions. A Logic "1" present at the Load (LD) input will

cause a parallel transfer of data from the shift register to the

data latch. If the Load (LD) input is held high while data is

clocked into the shift register, the latch will be transparent.

All four logic inputs are TTL compatible on the HI-8010 and

CMOS compatible on the HI-8110.

on the rising edge of the Clock (CL). Clock (CL), Load (LD)

and Chip Select (CS) should be tied in common with each

other, respectively, between all cascaded display drivers.

INTERNAL OSCILLATOR CIRCUIT

To display segments, a Logic "1" is stored in the appropriate

shift register bit position, and the segment output is out-of-

phase with the backplane.

The backplane output functions in 1 of 2 modes; externally

driven or self-oscillating. When the LCDØ input is externally

driven with the LCDØOPT input open circuit (Figure 2), the

backplane output will be in-phase with LCDØ. Utilizing the

self-oscillating mode, inputs LCDØ and LCDØOPT are tied

together and connected to an RC circuit (Figure 3).

A 150KW resistor with a 470pF capacitor generates an

approximate backplane frequency of 100Hz. The

LCDØ/LCDØOPT oscillator frequency is divided by 256 to

determine the backplane output frequency. The resistor

value (R) must be at least 30KW for proper self-oscillator

operation.

LCDØ

LCDØ

OPT

For displays having a number of segments greater than 38,

two or more of the display drivers may be cascaded together

by connecting the serial data output (DOUT) from the first

driver, to the serial data input (DIN) of the following driver,

etc. (See Figures 2 & 3). Data out (DOUT) will change state

÷ 256

Q

TO BACKPLANE

TRANSLATOR

AND DRIVER

Figure 1

TIMING DIAGRAM

CL

INPUT

DIN

INPUT

CS

INPUT

LD

INPUT

DOUT

OUTPUT

VALID

tDS

tDH

tCSS

tCSH

tCL

tCDO

tLS

VALID

tLCS

tCSL

tLW

HOLT INTEGRATED CIRCUITS

3-4

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