X28HC64 查看數據表（PDF） - Renesas Electronics
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X28HC64 Datasheet PDF : 18 Pages
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X28HC64
Hardware Data Protection
The X28HC64 provides two hardware features that protect
nonvolatile data from inadvertent writes.
• Default VCC Sense—All write functions are inhibited when VCC is
3V typically.
• Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will
prevent an inadvertent write cycle during power-up and
power-down, maintaining data integrity.
Software Data Protection
The X28HC64 offers a software controlled data protection feature.
The X28HC64 is shipped from Intersil with the software data
protection NOT ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected during
power-up/power-down operations through the use of external
circuits. The host would then have open read and write access of the
device once VCC was stable.
The X28HC64 can be automatically protected during power-up
and power-down without the need for external circuits by
employing the software data protection feature. The internal
software data protection circuit is enabled after the first write
operation utilizing the software algorithm. This circuit is
nonvolatile and will remain set for the life of the device, unless
the reset command is issued.
Once the software protection is enabled, the X28HC64 is also
protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be issued
prior to writing additional data to the device.
Software Algorithm
Selecting the software data protection mode requires the host
system to precede data write operations by a series of three write
operations to three specific addresses. Refer to Figures 7 and 8
for the sequence. The 3-byte sequence opens the page write
window, enabling the host to write from 1 to 64 bytes of data.
Once the page load cycle has been completed, the device will
automatically be returned to the data protected state.
Regardless of whether the device has previously been protected
or not, once the software data protection algorithm is used, the
X28HC64 will automatically disable further writes unless another
command is issued to deactivate it. If no further commands are
issued, the X28HC64 will be write protected during power-down
and after any subsequent power-up.
Note: Once initiated, the sequence of write operations should not
be interrupted.
VCC
0V
(VCC)
DATA
ADDR
CE
WE
AAA
1555
55
0AAA
A0
1555
≤tBLC MAX
WRITES
OK
tWC
BYTE
OR
PAGE
WRITE
PROTECTED
FIGURE 7. TIMING SEQUENCE—BYTE OR PAGE WRITE
FN8109 Rev 4.00
June 27, 2016
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA A0
TO ADDRESS
1555
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
BYTE/PAGE
LOAD ENABLED
OPTIONAL
BYTE/PAGE
LOAD OPERATION
AFTER TWC
RE-ENTERS DATA
PROTECTED STATE
FIGURE 8. WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION
Page 6 of 18
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