EL7562 查看數據表（PDF） - Renesas Electronics
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EL7562 Datasheet PDF : 9 Pages
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EL7562
Closed-Loop AC Electrical Specifications
PARAMETER
DESCRIPTION
FOSC
tSYNC
MSS
tBRM
tLEB
DMAX
Oscillator Initial Accuracy
Minimum Oscillator Sync Width
Soft-start Slope
FET Break Before Make Delay
High Side FET Minimum On Time
Maximum Duty Cycle
VS = VIN = 5V, TA = TJ = 25°C, COSC = 270pF, unless otherwise specified.
CONDITIONS
MIN
TYP MAX UNIT
493
580
667
kHz
25
ns
0.5
V/ms
15
ns
150
ns
95
%
Pin Descriptions
PIN
NUMBER PIN NAME
PIN FUNCTION
1
SGND Control circuit negative supply
2
COSC Oscillator timing capacitor; FOSC can be approximated by: FOSC (kHz) = 0.1843/COSC, COSC in µF
3
VDD
Control circuit positive supply
4
PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET
5
PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET
6
VIN
Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
7
VIN
Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
8
EN
Chip enable, active high; a 2µA internal pull-up current enables the device if the pin is left open
9
PGND Ground return of the regulator
10
VHI
Positive supply of the high-side driver
11
LX
Inductor drive pin; high current digital output whose average voltage equals the regulator output voltage
12
LX
Inductor drive pin; high current digital output whose average voltage equals the regulator output voltage
13
VDRV Positive supply of the low-side driver and input voltage for the high-side boot strap
14
FB
Voltage feedback input; connected to an external resistor divider between VOUT and GND; a 125nA pull-up current
forces VOUT to VS in the event that FB is floating
15
VREF Bandgap reference bypass capacitor; typically 0.1µF to GND
16
PGND Ground return of the regulator
FN7295 Rev 1.00
May 1, 2006
Page 3 of 9
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