EL7562CU 查看數據表（PDF） - Renesas Electronics
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EL7562CU Datasheet PDF : 9 Pages
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EL7562
Slope compensation is required to prevent system instability
that occurs in current-mode topologies operating at duty-cycles
greater than 50% and is also used to define the open-loop gain
of the overall system. The slope compensation is fixed
internally and optimized for 500mA inductor ripple current. The
power tracking will not contribute any input to the comparator
steady-state operation. Current feedback is measured by the
patented sensing scheme that senses the inductor current
flowing through the high-side switch whenever it is conducting.
At the beginning of each oscillator period the high-side NMOS
switch is turned on. The comparator inputs are gated off for a
minimum period of time of about 150ns (LEB) after the high-
side switch is turned on to allow the system to settle. The
Leading Edge Blanking (LEB) period prevents the detection of
erroneous voltages at the comparator inputs due to switching
noise. If the inductor current exceeds the maximum current
limit (ILMAX) a secondary over-current comparator will
terminate the high-side switch on time. If ILMAX has not been
reached, the feedback voltage FB derived from the regulator
output voltage VOUT is then compared to the internal feedback
reference voltage. The resultant error voltage is summed with
the current feedback and slope compensation ramp. The high-
side switch remains on until all four comparator inputs have
summed to zero, at which time the high-side switch is turned
off and the low-side switch is turned on. However, the
maximum on-duty ratio of the high-side switch is limited to
95%. In order to eliminate cross-conduction of the high-side
and low-side switches a 15ns break-before-make delay is
incorporated in the switch drive circuitry. The output enable
(EN) input allows the regulator output to be disabled by an
external logic control signal.
Output Voltage Setting
In general:
VOUT
=
0.985
1
+
RR-----21-
For VIN = 5V
VOUT
=
0.975
1
+
RR-----21-
FOR VIN = 3.3V
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and loop-
gain is changed. This is shown in the performance curves. A
100nA pull-up current from FB to VDD forces VOUT to GND in
the event that FB is floating.
NMOS Power FETs and Drive Circuitry
The EL7562 integrates low on-resistance (60m) NMOS FETs
to achieve high efficiency at 2A. In order to use an NMOS
switch for the high-side drive it is necessary to drive the gate
voltage above the source voltage (LX). This is accomplished
by bootstrapping the VHI pin above the LX voltage with an
external capacitor CVHI and internal switch and diode. When
the low-side switch is turned on and the LX voltage is close to
GND potential, capacitor CVHI is charged through internal
switch to VDRV, typically 5V. At the beginning of the next cycle
the high-side switch turns on and the LX pins begin to rise from
GND to VIN potential. As the LX pin rises the positive plate of
capacitor CVHI follows and eventually reaches a value of
VDRV+VIN, typically 10V, for VDRV=VIN=5V. This voltage is
then level shifted and used to drive the gate of the high-side
FET, via the VHI pin. A value of 0.1µF for CVHI is
recommended.
Reference
A 1.5% temperature compensated bandgap reference is
integrated in the EL7562. The external VREF capacitor acts as
the dominant pole of the amplifier and can be increased in size
to maximize transient noise rejection. A value of 0.1µF is
recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 95%.
Operating frequency can be adjusted through the COSC pin or
can be driven by an external source. If the oscillator is driven
by an external source care must be taken in selecting the ramp
amplitude. Since CSLOPE value is derived from the COSC
ramp, changes to COSC ramp will change the CSLOPE
compensation ramp which determine the open-loop gain of the
system.
When external synchronization is required, always choose
COSC such that the free-running frequency is at least 20%
lower than that of sync source to accommodate component
and temperature variations. Figure 1 shows a typical
connection.
External
Oscillato
100p BAT54
1
16
2
15
3
14
6
11
7
10
8
9
EL7562
FIGURE 1. OSCILLATOR SYNCHRONIZATION
FN7295 Rev 1.00
May 1, 2006
Page 8 of 9
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