DS1220AD 查看數據表（PDF） - Unspecified
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DS1220AD Datasheet PDF : 7 Pages
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POWER-DOWN/POWER-UP CONDITION
DS1220Y
16K Nonvolatile SRAM
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
at VIH before Power-Down
VCC Slew from VTP to 0V
Vcc Slew from 0V to VTP
at VIH after Power -Up
SYMBOL
tPD
tF
tR
tREC
MIN
MAX
UNITS
NOTES
0
µs
11
100
µs
0
µs
2
ms
PARAMETER
Expected Data Retention Time
SYMBOL
tDR
(TA=25℃)
MIN
MAX
UNITS NOTES
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. is high for a read cycle.
2. = VIH or VIL. If = VIH during a write cycle, the output buffers remain in a high impedance state.
3.tWP is specified as the logical AND of
and . tWP is measured from the latter of
or going low to the earlier of
or
going high.
4.tDS are measured from the earlier of
or going high.
5.These parameters are sampled with a 5 pF load and are not 100% tested.
6.If the
low transition occurs simultaneously with or later than the low transition in write cycle 1, the output buffers remain in a
high impedance state during this period.
7.If the
high transition occurs prior to or simultaneously with the high transition, the output buffers remain in a high
impedance state during this period.
8.If is low or the low transition occurs prior to or simultaneously with the
low transition, the output buffers remain in a high
impedance state during this period.
9.Each DS1220Y is marked with a 4-digit date code AABB. AA designates the year of manufacture. BB designates the week of
manufacture. The expected tDR is defined as starting at the date of manufacture.
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