DS17285-5 查看數據表（PDF） - Maxim Integrated

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DS17285-5

Real-Time Clocks

Maxim Integrated 

DS17285/DS17287/

DS17485/DS17487/

DS17885/DS17887

Register B (0Bh)

MSB

BIT 7

SET

BIT 6

PIE

BIT 5

AIE

BIT 4

UIE

Bit 7: SET. When the SET bit is 0, the update transfer

functions normally by advancing the counts once per sec-

ond. When the SET bit is written to 1, any update transfer

is inhibited, and the program can initialize the time and

calendar bytes without an update occurring in the midst

of initializing. Read cycles can be executed in a similar

manner. SET is a read/write bit and is not affected by any

internal functions of the DS17x85.

Bit 6: Periodic Interrupt Enable (PIE). This bit is a read/

write bit that allows the periodic interrupt flag (PF) bit in

Register C to drive the IRQ pin low. When PIE is set to 1,

periodic interrupts are generated by driving the IRQ pin low

at a rate specified by the RS3–RS0 bits of Register A. A 0

in the PIE bit blocks the IRQ output from being driven by

a periodic interrupt, but the PF bit is still set at the periodic

rate. PIE is not modified by any internal DS17x85 functions.

Bit 5: Alarm Interrupt Enable (AIE). This bit is a read/

write bit that, when set to 1, permits the alarm flag (AF)

bit in Register C to assert IRQ. An alarm interrupt occurs

for each second that the three time bytes equal the three

alarm bytes, including a don’t care alarm code of binary

11XXXXXX. When the AIE bit is set to 0, the AF bit does

not initiate the IRQ signal. The internal functions of the

DS17x285/87 do not affect the AIE bit.

Bit 4: Update-Ended Interrupt Enable (UIE). This bit is

a read/write bit that enables the update-end flag (UF) bit

in Register C to assert IRQ. The SET bit going high clears

the UIE bit.

Real-Time Clocks

BIT 3

SQWE

BIT 2

DM

BIT 1

24/12

LSB

BIT 0

DSE

Bit 3: Square-Wave Enable (SQWE). When this bit is set

to 1 and E32k = 0, a square-wave signal at the frequency

set by RS3–RS0 is driven out on the SQW pin. When the

SQWE bit is set to 0 and E32k = 0, the SQW pin is held

low. SQWE is a read/write bit. SQWE is set to 1 when

VCC is powered up.

Bit 2: Data Mode (DM). This bit indicates whether time

and calendar information is in binary or BCD format. The

program sets the DM bit to the appropriate format and can

be read as required. This bit is not modified by internal

functions. A 1 in DM signifies binary data, while a 0 in DM

specifies binary-coded decimal (BCD) data.

Bit 1: 24/12 Control (24/12). This bit establishes the for-

mat of the hours byte. A 1 indicates the 24-hour mode and

a 0 indicates the 12-hour mode. This bit is read/write and

is not affected by internal functions.

Bit 0: Daylight Saving Enable (DSE). This bit is a read/

write bit that enables two daylight saving adjustments

when DSE is set to 1. On the first Sunday in April, the

time increments from 1:59:59AM to 3:00:00AM. On

the last Sunday in October when the time first reaches

1:59:59AM, it changes to 1:00:00AM. When DSE is

enabled, the internal logic tests for the first/last Sunday

condition at midnight. If the DSE bit is not set when the

test occurs, the daylight saving function does not operate

correctly. These adjustments do not occur when the DSE

bit is zero. This bit is not affected by internal functions.

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