DS17285-5 查看數據表（PDF） - Maxim Integrated

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DS17285-5

Real-Time Clocks

Maxim Integrated 

DS17285/DS17287/

DS17485/DS17487/

DS17885/DS17887

Periodic Interrupt Selection

The periodic interrupt causes the IRQ pin to go to an

active state from once every 500ms to once every 122μs.

This function is separate from the alarm interrupt, which

can be output from once per second to once per day. The

periodic interrupt rate is selected using the same Register

A bits that select the squarewave frequency (see Table 4).

Changing the Register A bits affects both the square-wave

frequency and the periodic interrupt output. However,

each function has a separate enable bit in Register B.

The SQWE and E32k bits control the square-wave output.

Similarly, the periodic interrupt is enabled by the PIE bit in

Register B. The periodic interrupt can be used with soft-

ware counters to measure inputs, create output intervals,

or await the next needed software function.

Update Cycle

The DS17x85 executes an update cycle once per second

regardless of the SET bit in Register B. When the SET

bit in Register B is set to 1, the user copy of the double-

buffered time, calendar, and alarm bytes is frozen and

does not update as the time increments. However, the

time countdown chain continues to update the internal

copy of the buffer. This feature allows time to maintain

accuracy independent of reading or writing the time, cal-

endar, and alarm buffers, and also guarantees that time

and calendar information is consistent. The update cycle

also compares each alarm byte with the corresponding

Real-Time Clocks

time byte and issues an alarm if a match or if a don’t care

code is present in all alarm locations.

There are three methods that can handle access of the

RTC that avoid any possibility of accessing inconsistent

time and calendar data. The first method uses the update-

ended interrupt. If enabled, an interrupt occurs after every

update cycle that indicates that over 999ms are available

to read valid time and date information. If this interrupt is

used, the IRQF bit in Register C should be cleared before

leaving the interrupt routine.

A second method uses the update-in-progress (UIP) bit in

Register A to determine if the update cycle is in progress.

The UIP bit pulses once per second. After the UIP bit goes

high, the update transfer occurs 244μs later. If a low is

read on the UIP bit, the user has at least 244μs before the

time/calendar data is changed. Therefore, the user should

avoid interrupt service routines that would cause the time

needed to read valid time/calendar data to exceed 244μs.

The third method uses a periodic interrupt to determine if

an update cycle is in progress. The UIP bit in Register A

is set high between the setting of the PF bit in Register C

(see Figure 4). Periodic interrupts that occur at a rate of

greater than tBUC allow valid time and date information to

be reached at each occurrence of the periodic interrupt.

The reads should be complete within 1 (tPI/2 + tBUC) to

ensure that data is not read during the update cycle.

UIP

tBUC

UF

PF

tBUC = DELAY TIME BEFORE UPDATE CYCLE = 244µs.

Figure 4. UIP and Periodic Interrupt Timing

1 SECOND

t PI

tPI/2

tPI/2

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