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DS1831CS 查看數據表(PDF) - Maxim Integrated

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DS1831CS
MaximIC
Maxim Integrated MaximIC
DS1831CS Datasheet PDF : 15 Pages
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DS1831C/D/E
OPERATION—WATCHDOG TIMER
The watchdog timer function (DS1831D only) forces the WDS signal active (low) when the ST input
does not have a transition (high-to-low or low-to-high) within the predetermined time period. The
time-out period is determined by the condition of the TDWD pin (see Table 1). If TDWD is connected to
ground the minimum watchdog time-out would be 10ms, TD floating would yield a minimum time-out of
100ms, and TDWD connected to VCC would provide a time-out of 1000ms minimum. Time-out of the
watchdog starts when at least one of the RST outputs becomes inactive (high). If a transition occurs on
the ST input pin prior to time-out, the watchdog timer is reset and begins to time-out again. If the
watchdog timer is allowed to time-out, then the WDS output is pulsed active for a minimum of 100µs.
The WDS output is an open-drain output and must be pulled up externally. In most applications this
output would be connected to one of the Pushbutton inputs and would not require an external pull-up
resistor. The value of the resistors is not critical in most cases but must be set low enough to pull the
output to a high state. A common value used is 10kW. If a WDS output is connected to a pushbutton input
an additional pull-up resistor can be used (to improve speed of transitions) but is not required.
The ST input can be derived from many microprocessor outputs. The most typical signals used are the
microprocessor address signals, data signals, or control signals. When the microprocessor functions
normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to time-out. To
guarantee that the watchdog timer does not time-out, a transition must occur at or less than the minimum
times shown in Table 1. A typical circuit example is shown in Figure 10. The watchdog timing is shown
in Figure 11.
The DS1831A watchdog function cannot be disabled. The watchdog strobe input must be strobed to avoid
a watchdog time-out however the watchdog status output can be disconnected yielding the same result.
WATCHDOG CIRCUIT EXAMPLE Figure 10
VSENSE1
VCC
R1
PBRST2.5V
PBRST3.3V
IN1
NMI1
R2
µP
DS1831D
ST
WDS
GND
TDWD
10 kW
10 of 15

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