PEB2047 查看數據表（PDF） - Infineon Technologies

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产品描述 (功能)

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PEB2047

Memory Time Switch Large

Infineon Technologies 

3.4 Frame Evaluation

Suppose the following timing at PCM input IN5 (mode 2):

SP

CLK

FS 5

IN 5

TS 127

TS 0

PEB 2047

PEB 2047-16

ITD03773

Figure 9

If the device is in synchronized state (STAR:PSS = 1) and the command “frame evaluation at FS5”

(CMDR = 58H) is programmed, the second following rising edge of FS5 is evaluated and creates the

following result in register FER:

D (11) = 0

D (10:1) = 3E7H

D (0) = 0

D0 is fixed to 0 and doesn’t have a meaning in 8-MHz clock operation modes.

The actual offset of the incoming frame can now be calculated according to the formulas given in

table 9.

Semiconductor Group

19

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