EL7536 查看數據表（PDF） - Renesas Electronics
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EL7536 Datasheet PDF : 9 Pages
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EL7536
At extreme conditions (VIN < 3V, IO > 0.7A, and junction
temperature higher than 75°C), input cap C1 is
recommended to be 22µF. Otherwise, if any of the above 3
conditions is not true, C1 can remain as low as 10µF.
The RMS current present at the input capacitor is decided by
the following formula:
IINRMS = -----V----O-----------V--V--I--NI--N-----------V----O----- IO
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
IIL = ---V----IL--N---------V---V-I--N-O---------f--S--V----O---
• L is the inductance
• fS the switching frequency (nominally 1.4MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 1.5A surge current that can occur during a
current limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C4
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C4 should be sized to start the phase-
lead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow the equation
below:
fZ = 2--------R--1---2---C-----4-
Over a normal range of R2 (~10-100k), C4 will range from
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R1
and R2, which is solely determined by the desired output set
point. The equation below shows the pole frequency
relationship:
fP = -2----------R----1----1----R----2------C-----4-
Current Limit and Short-Circuit Protection
The current limit is set at about 1.5A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop below the preset voltage.
In the meantime, the excessive current heats up the
regulator until it reaches the thermal shut-down point.
Thermal Shut-Down
Once the junction reaches about 145°C, the regulator shuts
down. Both the P channel and the N channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about 130°C, the
regulator will restart again in the same manner as EN pin
connects to logic HI.
Thermal Performance
The EL7536 is in a fused-lead MSOP10 package. Compared
with regular MSOP10 package, the fused-lead package
provides lower thermal resistance. The JA is 100°C/W on a
4-layer board and 125°C/W on 2-layer board. Maximizing the
copper area around the pins will further improve the thermal
performance.
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
• Separate the Power Ground ( ) and Signal Ground ( );
connect them only at one point right at the pins
• Place the input capacitor as close to VIN and PGND pins
as possible
• Make the following PC traces as small as possible:
- from LX pin to L
- from CO to PGND
• If used, connect the trace from the FB pin to R1 and R2 as
close as possible
• Maximize the copper area around the PGND pin
• Place several via holes under the chip to additional ground
plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7536 Application Brief.
FN7396 Rev 8.00
July 13, 2006
Page 8 of 9
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