ADS-928 查看數據表（PDF） - DATEL Data Acquisition products

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ADS-928

500kHz, 14-Bit Sampling A/D Converters

DATEL Data Acquisition products  

ADS-928

500kHz, 14-Bit Sampling A/D Converters

TECHNICAL NOTES

1. Use external potentiometers to remove system errors or the small initial

errors to zero. Use a 20k trimming potentiometer for gain adjustment with

the wiper tied to pin 6 (ground pin 6 for operation without adjustments).

Use a 20k trimming potentiometer with the wiper tied to pin 5 for zero/

offset adjustment (connect pin 5 to pin 15, analog ground for operation

without adjustment).

2. Rated performance requires using good high-frequency circuit board

layout techniques. The analog and digital grounds are not connected

internally. Avoid ground-related problems by connecting the digital and

analog grounds to one point, the ground plane beneath the converter. Due

to the inductance and resistance of the power supply return paths, return

the analog and digital ground separately to the power supplies.

3. Bypass the analog and digital supplies and the +1OV reference (pin 1) to

ground with a 4.7μF, 25V tantalum electrolytic capacitor in parallel with

a 0.1 μF ceramic capacitor. Bypass the +10V reference (pin 1) to analog

ground (pin 15).

4. Obtain straight binary/offset binary output coding by tying COMP BIN (pin

8) to +5V or leaving it open. The device has an internal pull-up resistor

on this pin. To obtain complementary binary or complementary offset binary

output coding, tie the COMP BIN pin to ground. The COMP BIN signal is com-

patible to CMOS/TTL logic levels for those users desiring logic control of this

function.

5. To enable the three-state outputs, connect ENABLE (pin 9) to a logic ·"0"·

(low). To disable, connect ENABLE (pin 9) to a logic "1" (high).

6. The 200 ns minimum START CONVERT pulse width assures the hold mode

settling time requirements are met.

7. The specifications listed in Figure 2 (timing diagram) apply over the full

operating temperature range unless otherwise specified.

Table 2. Zero and Gain Adjust

FSR

0 to -10V

±5V

ZERO ADJUST +½ LSB

-305 μV

+305V

GAIN ADJUST FS - ½ LSB

-9.999085V

+4.999085V

CALIBRATION PROCEDURE

1. Connect the converter per Figure 3, and Table 1 for the appropriate full-

scale range (FSR). Apply a pulse of 200 nanoseconds minimum to the

START CONVERT input (pin 32) at a rate of 200kHz. This rate is chosen to

reduce flicker if LED's are used on the outputs for calibration purposes.

2. Zero Adjustments Apply a precision voltage reference source between

the analog input (pin 3) and signal ground (pin 4). Adjust the output of the

reference source per Table 2.

For unipolar, adjust the zero trimming potentiometer so that the output

code flickers equally between 00 0000 0000 0000 and 00 0000 0000

0001 with the COMP BIN (pin 8) tied high (straight binary) or between 11

1111 1111 1111 and 11 1111 1111 1110 with the pin 8 tied low (comple-

mentary binary).

For bipolar operation, adjust the potentiometer such that the code flickers

equally between 10 0000 0000 0000 and 10 0000 0000 0001 with pin

8 tied high (offset binary) or between 01 1111 1111 1111 and 01 1111

1111 1110 with pin 8 tied low (complementary offset binary).

Two's complement coding requires use of the MSB (pin 31) with pin 8 tied

high, adjusting the potentiometer such that the code flickers between 00

0000 0000 0000 and 00 0000 0000 0001.

3. Full-Scale Adjustment

Set the output of the voltage reference used in step 2 to the value shown

in Table 2.

Adjust the gain trimming potentiometer so that the output code flickers

equally between 11 1111 1111 1110 and 11 1111 1111 1111 for pin 8

tied high (straight binary) or between 00 0000 0000 0000 and 00 0000

0000 0001 for pin 8 tied low (complementary binary).

Two's complement coding requires use of the MSB (pin 31) with the pin 8

tied high, adjusting the gain trimming potentiometer so that the output code

flickers equally between 01 1111 1111 1110 and 01 1111 1111 1111.

4. To confirm proper operation of the device, vary the precision reference

voltage source to obtain the output coding listed in Table 3.

START

CONVERT

N

S/H

CONTROL

OUT

(INTERNAL)

A/D EOC

OUT

OUTPUT

DATA

ENABLE

HOLD MODE SETTLING

280ns min.

S/H ACQ. TIME

HOLD

10ns min., 25ns max.

30ns min.

SAMPLE

EOC

BUSY

20ns min., 35ns max.

700ns min.

DATA N-1 VALID

25ns min.

DATA N VALID

INVALID

10ns max. DATA INHIBITED

10ns max.

ENABLED DATA N VALID

NOTES: NOT DRAWN TO SCALE

Retriggering START CONVERT before EOC

goes low will not start a new conversion.

Figure 2. ADS-928 Timing Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com

27 Jul 2015 MDA_ADS-928.B02 Page 3 of 4

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