74VHC02PW 查看數據表（PDF） - Nexperia B.V. All rights reserved

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74VHC02PW

Quad 2-input NOR gate

Nexperia B.V. All rights reserved 

Nexperia

74VHC02; 74VHCT02

Quad 2-input NOR gate

12. Abbreviations

Table 10. Abbreviations

Acronym

CDM

CMOS

DUT

ESD

HBM

LSTTL

MM

TTL

Description

Charged Device Model

Complementary Metal-Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Low-power Schottky Transistor-Transistor Logic

Machine Model

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

74VHC_VHCT02 v.2

Modifications:

74VHC_VHCT02_1

Release date Data sheet status

20200415

Product data sheet

Change notice Supersedes

-

74VHC_VHCT02_1

• The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4: Derating values for Ptot total power dissipation updated.

• Package outline drawing SOT762-1 (DHVQFN14) updated.

20090813

Product data sheet

-

-

74VHC_VHCT02

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 15 April 2020

© Nexperia B.V. 2020. All rights reserved

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