A29400BUV-55F 查看數據表（PDF） - AMIC Technology
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A29400BUV-55F
AMIC Technology
A29400BUV-55F Datasheet PDF : 34 Pages
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A29400B Series
Features
5.0V ± 10% for read and write operations
Access time:
- 55ns (max.)
Current:
- 20mA typical active read current
- 30mA typical program/erase current
- 6μA typical CMOS standby
Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX7 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that
sector
Extended operating temperature range: -40°C~+85°C
for –U series
Top or bottom boot block configurations available
Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
Minimum 100,000 program/erase cycles per sector
20-year data retention at 125ºC
- Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
Data Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes
the erase operation
Hardware reset pin (RESET )
- Hardware method to reset the device to reading array
data
Package options
- 48-pin TSOP (I)
- All Pb-free (Lead-free) products are RoHS2.0 compliant
General Description
The A29400B is a 5.0 volt only Flash memory organized as
524,288 bytes of 8 bits or 262,144 words of 16 bits each.
The A29400B offers the RESET function. The 512 Kbytes
of data are further divided into eleven sectors for flexible
sector erase capability. The 8 bits of data appear on I/O0 -
I/O7 while the addresses are input on A1 to A17; the 16 bits
of data appear on I/O0~I/O15. The A29400B is offered in 48-
pin TSOP package. This device is designed to be
programmed in-system with the standard system 5.0 volt
VCC supply. Additional 12.0 volt VPP is not required for in-
system write or erase operations. However, the A29400B
can also be programmed in standard EPROM programmers.
The A29400B has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29400B has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The
A29400B also offers the ability to program in the Erase
Suspend mode. The standard A29400B offers access time of
55ns, allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention the device
has separate chip enable ( CE ), write enable ( WE ) and
output enable ( OE ) controls.
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29400B is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O7 (Data Polling) and
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29400B is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program
data to, any other sector that is not selected for erasure.
True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data.
PRELIMINARY (June, 2016, Version 0.0)
1
AMIC Technology, Corp.
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