LP621024D-55LLTF 查看數據表（PDF） - AMIC Technology

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LP621024D-55LLTF

128K X 8 BIT CMOS SRAM

AMIC Technology 

Timing Waveforms (continued)

Write Cycle 2

(Chip Enable Controlled)

Address

CE1

CE2

WE

DIN

DOUT

(4)

tAS1

(4)

tWC

tAW

tCW5

tCW5

tWP2

tDW

tWHZ7

LP621024D-T Series

tWR3

tDH

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .

3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.

4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after

the WE transition, outputs remain in a high impedance state.

5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.

6. OE is continuously low. ( OE = VIL)

7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

(July, 2005, Version 1.2)

8

AMIC Technology, Corp.

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