ISL6210 查看數據表（PDF） - Renesas Electronics
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ISL6210 Datasheet PDF : 10 Pages
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ISL6210
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, Unless Otherwise Noted. (Continued)Parameters with
MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNITS
OUTPUT
Upper Drive Source Resistance
Upper Drive Source Current (Note 4)
Upper Drive Sink Resistance
Upper Drive Sink Current (Note 4)
Lower Drive Source Resistance
Lower Drive Source Current (Note 4)
Lower Drive Sink Resistance
Lower Drive Sink Current (Note 4)
NOTE:
RUG_SRC
IUG_SCR
RUG_SNK
IUG_SNK
RLG_SRC
ILG_SCR
RLG_SNK
ILG_SNK
250mA Source Current
VUGATE-PHASE = 2.5V
250mA Sink Current
VUGATE-PHASE = 2.5V
250mA Source Current
VLGATE = 2.5V
250mA Sink Current
VLGATE = 2.5V
-
1.0
2.5
-
2.00
-
A
-
1.0
2.5
2.00
-
A
-
1.0
2.5
-
2.00
-
A
-
0.4
1.0
-
4.00
-
A
3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
4. Limits established by characterization and are not production tested.
Functional Pin Description
NUMBER NAME
FUNCTION
1
GND Bias and reference ground. All signals are referenced to this node.
2
LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
3
PVCC This pin supplies power to both the lower and higher gate drives in ISL6210. Connect to a +5V supply. Place a high quality
low ESR ceramic capacitor from this pin to GND.
4
FCCM Logic control input that will force continuous conduction mode (HIGH state) or allow discontinuous conduction mode
(LOW state). Placing a series resistor in this input will allow the switching dead-time to be programmed.
5
PGND It is the power ground return of both low gate drivers.
6
LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
7
EN Logic control input that will enable (HIGH state) or disable (LOW state) the IC. Shutdown current is <1µA.
8
PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin
provides a return path for the upper gate drive.
9
UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
10
BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin and
the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap Diode”
on page 7 for guidance in choosing the capacitor value.
11
BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin and
the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See“Internal Bootstrap Diode”
on page 7 for guidance in choosing the capacitor value.
12
UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
13
PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin
provides a return path for the upper gate drive.
14
VCC Connect a +5V bias supply to this pin. It supplies the internal analog circuits. Place a high quality, low ESR ceramic capacitor
from this pin to GND. This should be a separate capacitor than the one used for PVCC (Pin 3).
15
PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation. See
“Three-State PWM Input” on page 6 for further details. Connect this pin to the PWM output of the controller.
16
PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation. See
“Three-State PWM Input” on page 6 for further details. Connect this pin to the PWM output of the controller.
N/A
PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
FN6392 Rev 1.00
December 9, 2008
Page 5 of 10
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