MC33984BPNA(2007) 查看數據表（PDF） - Freescale Semiconductor

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MC33984BPNA
(Rev.:2007)

Dual Intelligent High-Current Self-Protected Silicon High-Side Switch (4.0 mΩ)

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.

Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Control Interface

Input Logic High Voltage (13)

Input Logic Low Voltage (13)

Input Logic Voltage Hysteresis (14)

Input Logic Pull-down Current (SCLK, IN, SI)

RST Input Voltage Range

SO, FS Tri-State Capacitance (15)

Input Logic Pull-Down Resistor (RST) and WAKE

Input Capacitance (15)

WAKE Input Clamp Voltage (16)

ICL(WAKE) < 2.5 mA

VIH

VIL

VIN[0:1] (HYS)

IDWN

VRST

CSO

RDWN

CIN

VCL(WAKE)

0.7 VDD

–

100

5.0

4.5

–

100

–

7.0

–

–

V

–

0.2 VDD

V

600

1200

mV

–

20

µA

5.0

5.5

V

–

20

pF

200

400

kΩ

4.0

12

pF

V

–

14

WAKE Input Forward Voltage

ICL(WAKE) = - 2.5 mA

VF(WAKE)

- 2.0

V

–

- 0.3

SO High-State Output Voltage

IOH = 1.0 mA

FS, SO Low-State Output Voltage

IOL = -1.6 mA

VSOH

VSOL

0.8 VDD

–

–

0.2

V

–

V

0.4

SO Tri-State Leakage Current

CS > 0.7 VDD

Input Logic Pull-Up Current (17)

CS, VIN[0:1] > 0.7 VDD

ISO(LEAK)

IUP

- 5.0

5.0

µA

0

5.0

µA

–

20

FSI Input Pin External Pull-down Resistance

FSI Disabled, HS[0:1] Indeterminate

FSI Enabled, HS[0:1] OFF

FSI Enabled, HS0 ON, HS1 OFF

FSI Enabled, HS[0:1] ON

RFS

RFSdis

RFSoffoff

RFSonoff

RFSonon

kΩ

–

0

1.0

6.0

6.5

7.0

15

17

19

40

Infinite

–

Notes

13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST

signals may be supplied by a derived voltage reference to VPWR.

14. No hysteresis on FSI and wake pins. Parameter is guaranteed by processing monitoring but is not production tested.

15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.

16. The current must be limited by a series resistance when using voltages > 7.0 V.

17. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD.

33984

10

Analog Integrated Circuit Device Data

Freescale Semiconductor

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