ISL8204M 查看數據表（PDF） - Renesas Electronics

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ISL8204M

Complete High Efficiency DC/DC Power Module

Renesas Electronics 

ISL8204M, ISL8206M

Note: ISL8204M, ISL8206M has integrated 9.76k resistance into

the module (dividing resistor for top side). The resistance

corresponding to different output voltages is as shown in Table 2:

TABLE 2. RESISTANCE TO OUTPUT VOLTAGES

VOUT

0.6V

0.8V

1.05V

RFB

open

28.7k

13k

1.2V

9.76k

VOUT

1.5V

1.8V

2.5V

3.3V

RFB

6.49k 4.87k 3.09k 2.16k

VOUT

RFB

5V

1.33k

6V

1.07k

Initialization (POR and OCP Sampling)

Figure 17 shows a start-up waveform of ISL8204M, ISL8206M.

The power-on-reset (POR) function continually monitors the bias

voltage at the PVCC pin. Once the rising POR threshold has

exceeded 4V (VPORR nominal), the POR function initiates the

overcurrent protection (OCP) sample and hold operation (while

COMP/EN is ~1V). When the sampling is complete, VOUT begins

the soft-start ramp.

PVCC

bias regulator can turn on cleanly. At the same time, the ISET pin

is initialized by disabling the low-side gate driver and drawing ISET

(nominal 21.5µA) through RSETI. This sets up a voltage that will

represent the ISET trip point. At t2, there is a variable time period

for the OCP sample and hold operation (0.0ms to 3.4ms

nominal; the longer time occurs with the higher overcurrent

setting). The sample and hold operation uses a digital counter

and DAC to save the voltage, so the stored value does not

degrade, as long as the PVCC is above VPORR (see “Overcurrent

Protection (OCP)” on page 12 for more details on the equations

and variables). Upon the completion of sample and hold at T3,

the soft-start operation is initiated, and the output voltage ramps

up between t4 and t5.

COOMMPP/E/NEN

Tt00

Tt11

IISSEETT

VVOOUUT T

FIGURE 18. ISET AND SOFT-START OPERATION

VOUT

~4V

COMP/EN

START SWITCHING

FIGURE 17. POR AND SOFT-START OPERATION

t1

t2 t3

t4

t5

COMP/EN

ISET

If the COMP/EN pin is held low during power-up, the initialization

will be delayed until the COMP/EN is released and its voltage

rises above the VENDIS trip point.

Figures 18 and 19 show a typical power-up sequence in more

detail. The initialization starts at t0, when either PVCC rises above

VPORR, or the COMP/EN pin is released (after POR). The

COMP/EN will be pulled up by an internal 20µA current source,

however, the timing will not begin until the COMP/EN exceeds

the VENDIS trip point (at t1). The external capacitance of the

disabling device, as well as the compensation capacitors, will

determine how quickly the 20µA current source will charge the

COMP/EN pin. With typical values, it should add a small delay

compared to the soft-start times. The COMP/EN will continue to

ramp to ~1V.

From t1, there is a nominal 6.8ms delay, which allows the PVCC

pin to exceed 6.5V (if rising up towards 12V), so that the internal

VOUT

3.4ms

3.4ms

FIGURE 19. ISET AND SOFT-START OPERATION

Soft-Start and Pre-Biased Outputs

The soft-start internally ramps the reference on the non-inverting

terminal of the error amp from 0V to 0.6V in a nominal 6.8ms.

The output voltage will follow the ramp from zero to its final value

in the same 6.8ms (the actual ramp seen on VOUT will be less

than the nominal time), due to some initialization timing

between t3 and t4.

FN6999 Rev 4.00

October 28, 2014

Page 10 of 19

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