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ISL85001

1A Standard Buck PWM Regulator

Renesas Electronics 

ISL85001

Detailed Description

The ISL85001 combines a standard buck PWM controller with an

integrated switching MOSFET. The buck controller drives an

internal N-channel MOSFET and requires an external diode to

deliver load current up to 1A. A Schottky diode is recommended

for improved efficiency and performance over a standard diode.

The standard buck regulator can operate from either an

unregulated DC source, such as a battery, with a voltage ranging

from +5.5V to +25V, or from a regulated system rail of +5V.

When operating from +5.5V or greater, the controller is biased

from an internal +5V LDO voltage regulator. The converter output

is regulated down to 0.6V from either input source. These

features make the ISL85001 ideally suited for FPGA and wireless

chipset power applications.

The PWM control loop uses a single output voltage loop with

input voltage feed-forward, which simplifies feedback loop

compensation and rejects input voltage variation. External

feedback loop compensation allows flexibility in output filter

component selection. The regulator switches at a fixed 500kHz.

The buck regulator is equipped with a lossless current limit

scheme. The current limit in the buck regulator is achieved by

monitoring the drain-to-source voltage drop of the internal

switching power MOSFET. The current limit threshold is internally

set at 1.7A. The part also features undervoltage protection by

latching the switching MOSFET driver to the OFF-state during an

overcurrent, when the output voltage is lower than 75% of the

regulated output. This helps minimize power dissipation during a

short-circuit condition. Due to only the switching power MOSFET

integration, there is no overvoltage protection feature for this

part.

+5V Internal Bias Supply (VDD)

Voltage applied to the VIN pin with respect to GND is regulated to

+5V DC by an internal LDO regulator. The output of the LDO, VDD,

is the bias voltage used by all the internal control and protection

circuitry. The VDD pin requires a ceramic capacitor connected to

GND. The capacitor serves to stabilize the LDO and to decouple

load transients.

The input voltage range for the ISL85001 is specified as +5.5V to

+25V or +5V ±10%. In the case of an unregulated supply case,

the power supply is connected to VIN only. Once enabled, the

linear regulator will turn-on and rise to +5V on VDD. In the +5V

supply case, the VDD and VIN pins must be tied together to

bypass the LDO. The external decoupling capacitor is still

required in this mode.

Operation Initialization

The power-on reset circuit and enable inputs prevent false

start-up of the PWM regulator output. Once all the input criteria

are met, the controller soft-starts the output voltage to the

programmed level.

Power-On Reset and Undervoltage Lockout

The PWM portion of the ISL85001 automatically initializes upon

receipt of input power. The Power-On Reset (POR) function

continually monitors the VDD voltage. While below the POR

thresholds, the controller inhibits switching off the internal power

FN6769 Rev.3.00

Apr 14, 2017

MOSFET. Once exceeded, the controller initializes the internal

soft-start circuitry. If either input supply drops below their falling

POR threshold during soft-start or operation, the buck regulator

latches off.

Enable and Disable

All internal power devices are held in a high-impedance state,

which ensures they remain off while in shutdown mode. Typically,

the enable input for a specific output is toggled high after the

input supply to that regulator is active and the internal LDO has

exceeded its POR threshold.

The EN pin enables the buck controller portion of the ISL85001.

When the voltage on the EN pin exceeds the POR rising

threshold, the controller initiates the soft-start function for the

PWM regulator. If the voltage on the EN pin drops below the POR

falling threshold, the buck regulator shuts down.

Pulling the EN pin low simultaneously puts the output into

shutdown mode and supply current drops to 100µA typical.

Soft-Start

Once the input supply latch and enable threshold are met, the

soft-start function is initialized. The soft-start circuitry begins

sourcing 30µA, from an internal current source, which charges the

external soft-start capacitor. The voltage on SS begins ramping

linearly from ground until the voltage across the soft-start

capacitor reaches 3.0V. This linear ramp is applied to the

noninverting input of the internal error amplifier and overrides the

nominal 0.6V reference. The output voltage reaches its regulation

value when the soft-start capacitor voltage reaches 1.6V. Connect

a capacitor from the SS pin to ground. This capacitor (along with

an internal 30µA current source) sets the soft-start interval of the

converter, tSS.

CSSF = 50  tSSs

(EQ. 1)

Upon disable, the SS pin voltage will discharge to zero voltage.

Power-Good

PG is an open-drain output of a window comparator that

continuously monitors the buck regulator output voltage. PG is

actively held low when EN is low and during the buck regulator

soft-start period. After the soft-start period terminates, PG becomes

high impedance as long as the output voltage is within ±12% of the

nominal regulation voltage set by FB. When VOUT drops 12% below

or rises 12% above the nominal regulation voltage, the ISL85001

pulls PG low. Any fault condition forces PG low until the fault

condition is cleared by attempts to soft-start. For logic level output

voltages, connect an external pull-up resistor between PG and VDD.

A 100kΩ resistor works well in most applications.

Output Voltage Selection

The regulator output voltages can be programmed using external

resistor dividers that scale the voltage feedback relative to the

internal reference voltage. The scaled voltage is fed back to the

inverting input of the error amplifier; refer to Figure 21.

The output voltage programming resistor, R4, will depend on the

value chosen for the feedback resistor, R1, and the desired output

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