ISL8200AM 查看數據表（PDF） - Renesas Electronics
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ISL8200AM Datasheet PDF : 25 Pages
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ISL8200AM
Pin Descriptions (Continued)
PIN #
6
7
8
9
10
11
12
13
14
16
17
18
19
20
21
22
PIN NAME
ISHARE
FSYNC_IN
CLKOUT
PH_CNTRL
ISHARE_BUS
FF
EN
VIN
PVCC
PHASE
PVIN
PGND
VOUT
OCSET
VCC
PGOOD
PIN DESCRIPTION
Analog current output. Cascaded system level overcurrent shutdown pin. Multi-module operation can be achieved by
connecting the ISHARE pin of two or more modules together. The common current share bus sums each of the modules'
average current contribution to the load to protect for an overcurrent condition at the load. The pin sources 15µA plus the
average module's output current. The shared bus voltage (VISHARE) is developed across an external resistor (RISHARE).
VISHARE represents the average current of all active channel(s) that are connected together.
The ISHARE bus voltage is compared with each module's internal reference voltage set by each module's RISET resistor. This
will generate an individual current share error signal in each cascaded controller. The share bus impedance RISHARE should
be set as RISET/NCTRL, RISET divided by the number of active current sharing controllers. The output current from this pin
generates a voltage across the external resistor. This voltage, VISHARE, is compared to an internal 1.2V threshold for average
overcurrent protection. For full-scale current, RISHARE should be ~10kΩ. Typically 10kΩ is used for RSHARE and RSET. The
output current range is 15µA to 126µA typical.
Analog input control pin. An optional external resistor (RFS-ext) connected to this pin and ground will increase the oscillator
switching frequency. The module has an internal 59kΩ resistor connected to the FSYNC_In pin for a default frequency of
700kHz. The internal oscillator will lock to an external frequency source when connected to a square waveform. The external
source is typically the CLKOUT signal from another ISL8200AM or an external clock. The internal oscillator synchronizes with
the leading positive edge of the input signal. The input voltage range for the external source is 0V to 5V square wave. When
not synchronized to an external clock, a 100pF capacitor between FSYNC_IN and PGND1 is recommended.
Digital voltage output. This pin provides a clock signal to synchronize with other ISL8200AM(s). When more than one
ISL8200AM is in the system, the two independent regulators can be programmed through PH_CNTRL for different degrees
of phase delay.
Analog input. The voltage level on this pin is used to program the phase shift of the CLKOUT clock signal to synchronize with
other module(s).
Open pin until the first PWM pulse is generated. Then, through an internal FET, this pin connects the module’s ISHARE to the
system’s ISHARE bus after pre-bias is complete and soft-start is initiated.
Analog voltage input. The voltage on this pin is fed into the controller, adjusting the sawtooth amplitude to generate the
feed-forward function. The input voltage range is 0.8V to VCC. Typically, FF is connected to EN.
This is a double function pin:
Analog input voltage - The input voltage to this pin is compared with a precision 0.8V reference and enables the digital soft-
start. The input voltage range is 0V to VCC or VIN through a pull-up resistor maintaining a typical current of 5mA.
Analog voltage output - This pin can be used as a voltage monitor for input bus undervoltage lockout. The hysteresis levels
of the lockout can be programmed through this pin using a resistor divider network. Furthermore, during fault conditions
(such as overvoltage, overcurrent, and over-temperature), this pin is used to communicate the information to other cascaded
modules by pulling the wired OR low as it is an open drain. The output voltage range is 0V to VCC.
Analog voltage input. This pin should be tied directly to the input rail when using the internal linear regulator. It provides power
to the internal linear drive circuitry. When used with an external 5V supply, this pin should be tied directly to PVCC. The internal
linear device is protected against the reversed bias generated by the remaining charge of the decoupling capacitor at VCC
when losing the input rail. The input voltage range is 4.5V to 20V.
Analog output. This pin is the output of the internal series linear regulator. It provides the bias for both low-side and high-side
drives. Its operational voltage range is 4.5V to 5.6V. The decoupling ceramic capacitor in the PVCC pin is 10µF.
Analog output. This pin is the phase node of the regulator. The output voltage range is 0V to 30V.
Analog input. This input voltage is applied to the power FETs with the FETs ground being the PGND pin. It is recommended to
place 22µF of input decoupling capacitance directly between the PVIN pin and the PGND pin as close as possible to the
module. The input voltage range is 3V to 20V.
All voltage levels are referenced to this pad. This is the low-side MOSFET ground. PGND and PGND1 should be connected
together with a ground plane.
Output voltage from the module. The output voltage range is 0.6V to 6V.
Analog input. This pin is used with the PHASE pin to set the current limit of the module. The input voltage range is 0V to 30V.
Analog input. This pin provides bias power for the analog circuitry. Its operational range is 4.5V to 5.6V. In 3.3V applications,
VCC, PVCC, and VIN should be shorted to allow operation at the low end input as it relates to the VCC falling threshold limit.
This pin can be powered either by the internal linear regulator or by an external voltage source.
Analog output. This pin, pulled up to VCC using an internal 10kΩ resistor, provides a power-good signal when the output is
within 9% of a nominal output regulation point with 4% hysteresis (13%/9%) and when soft-start is complete. An external
pull-up is not required. PGOOD monitors the outputs (VMON1) of the internal differential amplifiers. The output voltage range
is a 0V to VCC.
FN8271 Rev.7.00
Apr 27, 2018
Page 4 of 25
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