ISL62882 查看數據表（PDF） - Renesas Electronics

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ISL62882

Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

Renesas Electronics 

ISL62882, ISL62882B

Theory of Operation

Multiphase R3™ Modulator

VW

Master Clock Circuit

Master

Master COMP

Clock Phase

Clock Vcrm

Sequencer

gmVo

Crm

Clock1

Clock2

VW

VW

Crs1

Vcrs1

VW

Crs2

Vcrs2

Slave Circuit 1

Clock1

S

R

Q

PWM1

Phase1

L1

IL1

gm

Slave Circuit 2

Clock2

S

R

Q

PWM2

Phase2

L2

IL2

gm

Vo

Co

FIGURE 5. R3 MODULATOR CIRCUIT

VW

Vcrm

COMP

Master

Clock

Clock1

PWM1

Clock2

PWM2

VW

Hysteretic

Window

Vcrs2 Vcrs1

FIGURE 6. R3™ MODULATOR OPERATION PRINCIPLES IN

STEADY STATE

Since the ISL62882 works with Vcrs, which are large amplitude

and noise-free synthesized signals, the ISL62882 achieves lower

phase jitter than conventional hysteretic mode and fixed PWM

Vcrm

Master

Clock

Clock1

PWM1

Clock2

PWM2

VW

COMP

VW

Vcrs1

Vcrs2

FIGURE 7. R3 MODULATOR OPERATION PRINCIPLES IN LOAD

INSERTION RESPONSE

The ISL62882 is a multiphase regulator implementing Intel®

IMVP-6.5™ protocol. It can be programmed for 1- or 2-phase

operation for microprocessor core applications. It uses Intersil

patented R3™ (Robust Ripple Regulator™) modulator. The R3™

modulator combines the best features of fixed frequency PWM

and hysteretic PWM while eliminating many of their shortcomings.

Figure 5 conceptually shows the ISL62882 multiphase R3™

modulator circuit, and Figure 6 shows the operation principles.

A current source flows from the VW pin to the COMP pin, creating

a voltage window set by the resistor between the two pins. This

voltage window is called VW window in the following discussion.

Inside the IC, the modulator uses the master clock circuit to

generate the clocks for the slave circuits. The modulator

discharges the ripple capacitor Crm with a current source equal

to gmVo, where gm is a gain factor. Crm voltage Vcrm is a

sawtooth waveform traversing between the VW and COMP

voltages. It resets to VW when it hits COMP, and generates a

one-shot master clock signal. A phase sequencer distributes the

master clock signal to the slave circuits. If the ISL62882 is in

2-phase mode, the master clock signal will be distributed to

Phases 1 and 2, and the Clock1 and Clock2 signals will be 180°

out-of-phase. If the ISL62882 is in 1-phase mode, the master

clock signal will be distributed to Phases 1 only and be the

Clock1 signal.

Each slave circuit has its own ripple capacitor Crs, whose voltage

mimics the inductor ripple current. A gm amplifier converts the

inductor voltage into a current source to charge and discharge

Crs. The slave circuit turns on its PWM pulse upon receiving the

clock signal, and the current source charges Crs. When Crs

voltage VCrs hits VW, the slave circuit turns off the PWM pulse,

and the current source discharges Crs.

mode controllers. Unlike conventional hysteretic mode

converters, the ISL62882 has an error amplifier that allows the

controller to maintain a 0.5% output voltage accuracy.

FN6890 Rev 4.00

June 21, 2011

Page 11 of 41

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