HSP43220 查看數據表（PDF） - Renesas Electronics

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HSP43220

Decimating Digital Filter

Renesas Electronics 

HSP43220

Integrator Section

The data from the shifter goes to the Integrator section.

This is a cascade of 5 integrator (or accumulator) stages,

which implement a low pass filter. Each accumulator is

implemented as an adder followed by a register in the feed

forward path. The integrator is clocked by the sample clock,

CK_IN as shown in Figure 2. The bit width of each integrator

stage goes from 66 bits at the first integrator down to 26 bits

at the output of the fifth integrator. Bit truncation is performed

at each integrator stage because the data in the integrator

stages is being accumulated and thus is growing, therefore

the lower bits become insignificant, and can be truncated

without losing significant data.

There are three signals that control the integrator section;

they are H_STAGES, H_BYP and RESET. In Figure 2 these

control signals have been decoded and are labelled

INT_EN1 - INT_EN5. The order of the filter is loaded via the

control bus and is called H_STAGES. H_STAGES is

decoded to provide the enables for each integrator stage.

When a given integrator stage is selected, the feedback path

is enabled and the integrator accumulates the current data

sample with the previous sum. The integrator section can be

put in bypass mode by the H_BYP bit. When H_BYP or

RESET is asserted, the feedback paths in all integrator

stages are cleared.

Decimation Register

The output of the Integrator section is latched into the

Decimation Register by CK_DEC. The output of the

Decimation register is cleared when RESET is asserted. The

HDF decimation rate = H_DRATE +1, which is defined as

HDEC for convenience.

A0-1

WR CS C_BUS

CK_IN RESET

RESET CK_IN ASTARTIN

CONTROL

REGISTER LOGIC

H_DRATE

H_BYP

CLOCK

DIVIDER

ISTART

START

LOGIC

STARTIN

STARTOUT

6

5

5

H_GROWTH INT_EN1-5 COMB_EN1-5

CK DEC

ISTART

H_GROWTH

6

DATA

INPUT

DATA

IN 16 REG 16 SHIFTER 66

HDF FILTER SECTION

INT_EN1-5

RESET

COMB_EN1-5

5

5

INTEGRATOR

26

DEC

REG 26

COMB FILTER

19

RESET

ROUND

16

TO FIR

REG 16

CK_IN

CK_DEC

FIGURE 1. HIGH ORDER DECIMATION FILTER FIGURE

TO FIR

FROM

SHIFTER

66

CK IN

0

MUX

INT_EN5



REG

63

0

MUX

INT_EN4



REG

53

0

MUX

INT_EN3



REG

43

0

MUX

INT_EN2



REG

35

0

MUX

INT_EN1



REG

TO

DECIMATION

REGISTER

26

FIGURE 2. INTEGRATOR

FN2486 Rev 10.00

Oct 10, 2008

Page 4 of 21

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