HSP43220 查看數據表（PDF） - Renesas Electronics

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HSP43220

Decimating Digital Filter

Renesas Electronics 

HSP43220

DDF Control Registers (Continued)

FC_Register (A1 = 0, A0 = 1)

F_CF

C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4

X X X X X X X X X X X X C3 C2 C1 C0

15 14 13 12 11 10 9

876543210

F_CF

Bits C0-C19 represent the coefficient data, where C19 is the MSB. Two writes are

required to write each coefficient which is 2's complement fractional format. The first

write loads C19 through C4; C3 through C0 are loaded on the second write cycle. As

the coefficients are written into this register they are formatted into a 20-bit coefficient

and written into the Coefficient RAM sequentially starting with address location zero.

The coefficients must be loaded sequentially, with the center tap being the last

coefficient to be loaded. See “Coefficient RAM” on page 10.

FIGURE 5.

FN2486 Rev 10.00

Oct 10, 2008

Page 7 of 21

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