AD5273BRJZ1-R2 查看數據表（PDF） - Analog Devices

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AD5273BRJZ1-R2

64-Position OTP Digital Potentiometer

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5273

W1

8A

VDD 2 AD5273 7 B

TOP VIEW

GND 3 (Not to Scale) 6 AD0

SCL 4

5 SDA

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1

W

2

VDD

Wiper Terminal W. GND ≤ VW ≤ VDD.

Positive Power Supply. Specified for non-OTP operation from 2.7 V to 5.5 V. For OTP programming, VDD_OTP

must be set within the window of 5 V to 5.5 V for all end to end resistance options, and be capable of sourcing

100 mA.

3

GND

Common Ground.

4

SCL

5

SDA

6

AD0

Serial Clock Input. Requires a pull-up resistor. If it is driven directly from a logic controller without the pull-up

resistor, ensure that the VIH minimum is 0.7 × VDD.

Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the

pull-up resistor, ensure that the VIH minimum is 0.7 × VDD.

I2C Device Address Bit. Allows a maximum of two AD5273 devices to be addressed.

7

B

8

A

Resistor Terminal B. GND ≤ VB ≤ VDD.

Resistor Terminal A. GND ≤ VA ≤ VDD.

Rev. J | Page 7 of 20

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