P89LPC9107 查看數據表（PDF） - NXP Semiconductors.

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P89LPC9107

8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable flash with 8-bit A/D converter

NXP Semiconductors. 

NXP Semiconductors

P89LPC9102/9103/9107

8-bit microcontrollers with two-clock accelerated 80C51 core

I In-Application Programming (IAP-Lite) and byte erase allows code memory to be used

for non-volatile data storage.

I Serial flash ICP allows simple production coding with commercial EPROM

programmers. Flash security bits prevent reading of sensitive application programs.

I Watchdog timer with separate on-chip oscillator, requiring no external components.

The watchdog prescaler is selectable from eight values.

I Low voltage reset (Brownout detect) allows a graceful system shutdown when power

fails. May optionally be configured as an interrupt.

I Idle mode and two different reduced power Power-down modes. Improved wake-up

from Power-down mode (a LOW interrupt input starts execution). Typical Power-down

mode current is less than 1 µA (total Power-down mode with voltage comparators

disabled).

I Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A reset counter and reset glitch suppression circuitry prevent spurious

and incomplete resets. A software reset function is also available.

I Programmable port output configuration options: quasi-bidirectional, open drain,

push-pull, input-only.

I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of

the pins match or do not match a programmable pattern.

I LED drive capability (20 mA) on all port pins. A maximum limit is specified for the

entire chip.

I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns

minimum ramp times.

I Only power and ground connections are required to operate the

P89LPC9102/9103/9107 when internal reset option is selected.

I Four interrupt priority levels.

I Two keypad interrupt inputs.

I Second data pointer.

I External clock input.

I Clock output (P89LPC9102/9107).

I Schmitt trigger port inputs.

I Emulation support.

3. Product comparison overview

Table 1 highlights the differences between these two devices. For a complete list of device

features, please see Section 2 “Features”.

Table 1. Product comparison overview

Type number UART

T0 toggle/PWM

P89LPC9102

-

X

P89LPC9103

X

-

P89LPC9107

X

X

T1 toggle/PWM

X

-

X

CLKOUT

X

-

X

P89LPC9102_9103_9107_3

Product data sheet

Rev. 03 — 10 July 2007

© NXP B.V. 2007. All rights reserved.

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