AD9848AKST 查看數據表（PDF） - Analog Devices
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AD9848AKST Datasheet PDF : 32 Pages
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AD9848/AD9849
TIMING SPECIFICATIONS (CL = 20 pF, fCLI = 20 MHz (AD9848) or 30 MHz (AD9849), Serial Timing in Figures 3a and 3b,
unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK (CLI), AD9848
CLI Clock Period
CLI High/Low Pulsewidth
Delay From CLI to Internal Pixel Period Position
MASTER CLOCK (CLI), AD9849
CLI Clock Period
CLI High/Low Pulsewidth
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth
CLPOB Pulsewidth*
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge (AD9848)
SHP Rising Edge to SHD Rising Edge (AD9849)
DATA OUTPUTS
Output Delay from Programmed Edge
Pipeline Delay
tCLI
tADC
tCLIDLY
tCONV
tADC
tCDM
tCOB
tS1
tS1
tOD
50
25
6
33.33
16.67
4
10
2
20
20
13
6
9
ns
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
10
tLS
10
tLH
10
tDS
10
tDH
10
tDV
10
*Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
MHz
ns
ns
ns
ns
ns
–6–
REV. A
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