AD9954 查看數據表（PDF） - Analog Devices
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AD9954 Datasheet PDF : 40 Pages
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Parameter
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Current
Hysteresis
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High-Z Load
Logic 0 Voltage, High-Z Load
Propagation Delay
Output Duty-Cycle Error
Rise/Fall Time, 5 pF Load
Toggle Rate, High-Z Load
Output Jitter1
COMPARATOR NARROW-BAND SFDR
10 MHz to 160 MHz FOUT
Measured over a 1 MHz BW
Measured over a 250 kHz BW
Measured over a 50 kHz BW
Measured over a 10 Hz BW
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulse Width Low
Minimum Clock Pulse Width High
Maximum Clock Rise/Fall Time
Minimum Data Setup Time DVDD_I/O = 3.3 V
Minimum Data Setup Time DVDD_I/O = 1.8 V
Minimum Data Hold Time
Maximum Data Valid Time
Wake-Up Time2
Minimum Reset Pulse Width High
Test
Temp Level Min
25°C V
25°C IV
25°C I
25°C IV
30
Full VI
1.6
Full VI
25°C IV
25°C IV
25°C IV
25°C IV
200
25°C IV
25°C V
25°C V
25°C V
25°C V
Full IV
Full IV
7
Full IV
7
Full IV
Full IV
3
Full IV
5
Full IV
0
Full IV
Full IV
Full IV
5
I/O UPDATE, PS0, PS1 to SYNC_CLK Setup Time, DVDD_I/O = 3.3 V Full I
4
I/O UPDATE, PS0, PS1 to SYNC_CLK Setup Time, DVDD_I/O = 1.8 V Full I
6
I/O UPDATE, PS0, PS1 to SYNC_CLK Hold Time
Full I
0
Latency
I/O UPDATE to Frequency Change Prop Delay
25°C IV
24
I/O UPDATE to Phase Offset Change Prop Delay
25°C IV
24
I/O UPDATE to Amplitude Change Prop Delay
25°C IV
16
PS0, PS1 to RAM Driven Frequency Change Prop Delay
25°C IV
28
PS0, PS1 to RAM Driven Phase Change Prop Delay
25°C IV
28
PS0 to Linear Frequency Sweep Prop Delay
25°C IV
28
AD9954
Typ Max
3
500
±12
45
0.4
3
±5
1
1
80
85
90
95
25
2
25
1
Unit
pF
kΩ
μA
mV
V
V
ns
%
ns
MHz
ps rms
dBc
dBc
dBc
dBc
Mbps
ns
ns
ns
ns
ns
ns
ns
ms
SYSCLK
cycles3
ns
ns
ns
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
cycles
Rev. B | Page 5 of 40
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