AD7760BCP 查看數據表（PDF） - Analog Devices
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AD7760BCP Datasheet PDF : 22 Pages
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Preliminary Technical Data
AD7760
TIMING SPECIFICATIONS
Table 2. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, VDRIVE = TBD V, TA = +25°C, CLOAD = 25pF, Full Power Mode, unless otherwise noted
Parameter
fMCLK
fICLK
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
Limit at TMIN, TMAX
12.288
80
12.288
20
0.5 × tICLK
10
2
10
tICLK
tICLK
2
10
0.5 × tICLK
0.5 × tICLK
15
TBD
TBD
10
tICLK
tICLK
10
10
Unit
MHz min
MHz max
MHz min
MHz max
typ
nS min
nS min
nS typ
min
min
nS min
nS max
typ
typ
nS typ
xS min
xS min
nS max
xS min
xS min
nS min
nS min
Description
Applied Master Clock Frequency
Internal Modulator Clock Derived from MCLK.
DRDY Pulse Width
DRDY Falling Edge to CS falling Edge
RD/WR Setup Time to CS Falling Edge
Data Access Time
CS Low Pulse Width
CS High Pulse Width Between Reads
RD/WR Hold Time to CS Rising Edge
Bus Relinquish Time
DRDY High Period
DRDY Low Period
Data Access Time
Data Valid Prior to DRDY Rising Edge
Data Valid After DRDY Rising Edge
Bus Relinquish Time
CS Low Pulse Width
CS High Period Between Address and Data
Data Setup Time
Data Hold Time
1 tICLK = 1/fICLK
Rev. PrN | Page 5 of 22
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