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ADF4111(Rev0) 查看數據表（PDF） - Analog Devices

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ADF4111
(Rev.:Rev0)

RF PLL Frequency Synthesizers

Analog Devices

ADF4111 Datasheet PDF : 24 Pages

1 2 3 4 5 6 7 8 9 10 Next Last

ADF4110/ADF4111/ADF4112/ADF4113

Parameter

B Version B Chips2 Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4113 Phase Noise Floor7

Phase Noise Performance8

ADF4110: 540 MHz Output9

ADF4111: 900 MHz Output10

ADF4112: 900 MHz Output10

ADF4113: 900 MHz Output10

ADF4111: 836 MHz Output11

ADF4112: 1750 MHz Output12

ADF4112: 1750 MHz Output13

ADF4112: 1960 MHz Output14

ADF4113: 1960 MHz Output14

ADF4113: 3100 MHz Output15

Spurious Signals

ADF4110: 540 MHz Output9

ADF4111: 900 MHz Output10

ADF4112: 900 MHz Output10

ADF4113: 900 MHz Output10

ADF4111: 836 MHz Output11

ADF4112: 1750 MHz Output12

ADF4112: 1750 MHz Output13

ADF4112: 1960 MHz Output14

ADF4113: 1960 MHz Output14

ADF4113: 3100 MHz Output15

–171

–164

–91

–87

–90

–91

–78

–86

–66

–84

–85

–86

–97/–106

–98/–110

–91/–100

–100/–110

–81/–84

–88/–90

–65/–73

–80/–84

–80/–82

–171

–164

–91

–87

–90

–91

–78

–86

–66

–84

–85

–86

–97/–106

–98/–110

–91/–100

–100/–110

–81/–84

–88/–90

–65/–73

–80/–84

–82/–82

dBc/Hz typ

dBc typ

@ 25 kHz PFD Frequency

@ 200 kHz PFD Frequency

@ VCO Output

@ 1 kHz Offset and 200 kHz PFD Frequency

@ 300 Hz Offset and 30 kHz PFD Frequency

@ 1 kHz Offset and 200 kHz PFD Frequency

@ 200 Hz Offset and 10 kHz PFD Frequency

@ 1 kHz Offset and 200 kHz PFD Frequency

@ 1 kHz Offset and 1 MHz PFD Frequency

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

@ 30 kHz/60 kHz and 30 kHz PFD Frequency

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

@ 10 kHz/20 kHz and 10 kHz PFD Frequency

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

@ 1 MHz/2 MHz and 1 MHz PFD Frequency

NOTES

1Operating temperature range is as follows: B Version: –40°C to +85°C.

2The B Chip specifications are given as typical values.

3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency

which is less than this value.

4AVDD = DVDD = 3 V; For AVDD = DVDD = 5 V, use CMOS-compatible levels.

5Guaranteed by design.

6TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.

7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).

8The phase noise is measured with the EVAL-ADF411XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (See Table III).

9fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop B/W = 20 kHz.

10fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.

11fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz.

12fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.

13fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.

14fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.

15fREFIN = 10 MHz; fPFD = 1 MHz; Offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; Loop B/W = 20 kHz.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1 (AVDD = DVDD = 3 V ؎ 10%, 5 V ؎ 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V;

RSET = 4.7 k⍀; TA = TMIN to TMAX unless otherwise noted)

Parameter

Limit at TMIN to TMAX

(B Version)

Unit

Test Conditions/Comments

NOTES

1Guaranteed by design but not production tested.

Speciﬁcations subject to change without notice.

ns min

DATA to CLOCK Setup Time

DATA to CLOCK Hold Time

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Setup Time

LE Pulsewidth

REV. 0

–3–

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