ADSP-21367BBP-2A 查看數據表（PDF） - Analog Devices

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ADSP-21367BBP-2A

SHARC Processors

Analog Devices 

ADSP-21367/ADSP-21368/ADSP-21369

DATA MODES

The upper 32 data pins of the external memory interface are

muxed (using bits in the SYSCTL register) to support the exter-

nal memory interface data (input/output), the PDAP (input

only), the FLAGS (input/output), and the PWM channels (out-

put). Table 6 provides the pin settings.

Table 6. Function of Data Pins

Data Pin Mode

DATA31–16

DATA15–8

DATA7–0

000

EPDATA32–0

001

FLAGS/PWM15–01

EPDATA15–0

010

FLAGS/PWM15–01

FLAGS15–8

EPDATA7–0

011

FLAGS/PWM15–01

FLAGS15–0

100

PDAP (DATA + CTRL)

EPDATA7–0

101

PDAP (DATA + CTRL)

FLAGS7–0

110

Reserved

111

Three-state all pins

1 These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals

FLAGS/PWM_SEL. For more information, see the ADSP-21368 SHARC Processor Hardware Reference.

BOOT MODES

Table 7. Boot Mode Selection

BOOT_CFG1–0

00

01

10

11

Booting Mode

SPI Slave Boot

SPI Master Boot

EPROM/FLASH Boot

Reserved

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 4 on Page 18.

Table 8. Core Instruction Rate/CLKIN Ratio Selection

CLK_CFG1–0

00

01

10

11

Core to CLKIN Ratio

6:1

32:1

16:1

Reserved

Rev. C | Page 15 of 56 | January 2008

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